SMTS, IO/Clock Design Engineering

Micron • Boise, ID

2d • Onsite

About The Position

Micron Technology is seeking an experienced IO/Clocking Design Engineer at SMTS level to join their IP Design team. This role will contribute to the development of critical high-speed IP circuits used across Micron’s DRAM memory products. The engineer will be responsible for the architecture, design, development, optimization, verification, and technical support of these high-speed IPs. Key focus areas include equalization and bandwidth extension to push the limits of circuit and process performance, analyzing IO impairments, clock jitter, and duty cycle distortion, and assessing their impact on DRAM system timing. The role also involves developing core strategy and implementing effective engineering solutions to address these challenges. Relocation to Micron headquarters in Boise, Idaho is required.

Requirements

• Minimum MSEE + 10 years or BSEE + 12 years of industry experience with strong background in designing high-speed IO interface, timing and clocking circuits with proven silicon successes.
• Ability to supervise layout work and understand good layout practices for high-speed circuits to minimize parasitic impacts.
• Strong communication skills with the ability to convey sophisticated technical concepts to other design peers both verbally and written.
• Mental agility and ability to multi-task is a must for this position as we work with all product types (commodity, mobile, graphics) and product teams in parallel with silicon validation efforts.
• Demonstrated ability in mentoring and coaching engineers early in their careers.

Nice To Haves

• Prior experience in DRAM circuit design experience.
• Prior experience in channel modeling and characterization, transceiver noise and timing budget analysis, equalization techniques, SI knowledge, etc.
• Understanding of device physics and basic CMOS processing techniques.
• Demonstrated ability with AI/ML usage and fluency in scripting languages such as PERL/Python.

Responsibilities

• Define, innovate, design, optimize and verify high-speed IO and clocking circuits used in new DRAM products.
• Apply robust high-speed circuit design techniques and enhance critical performance evaluation, including timing and jitter sensitivity, of the IO data path and clock path at circuit and full-chip level.
• Develop accurate modeling, analysis and simulation methodology to capture key circuit performance metrics and their impact to product specifications at full-chip and system level.
• Work with Product Engineering and SI team to compare silicon performance with simulation results and support correlation activities.
• Collaborate with process integration and transistor modeling teams on Micron's next groundbreaking process node.

Benefits

• Choice of medical, dental and vision plans
• Benefit programs that help protect your income if you are unable to work due to illness or injury
• Paid family leave
• Robust paid time-off program
• Paid holidays

What This Job Offers

• Job Type: Full-time
• Career Level: Senior