The Qualcomm CHS (Central Hardware System) has exciting opportunities in the areas of signal integrity and power integrity in next generation server project. The candidate will work with IC, Package and PBC designers to find ways to optimize the overall System performance. The candidate’s first responsibility is working with substrate designers to make sure all system level constraints are met prior to the package Tape-out. The candidate is expected to communicate with PHY owners to understand the Specs for various IPs such as LP6, PCIe, 224G, etc, and also with PCB designers to assess the impact of Ball assignment to the system level performance. This position offers the opportunity to work across multiple organizations such as IP, PKG & PCB design and simulation teams.
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Job Type
Full-time
Career Level
Senior