Silicon Reverse Engineer

SemiAnalysis•Hillsboro, OR

3d•Hybrid

About The Position

SemiAnalysis is the leading independent research firm in semiconductors and AI. STEEL is our teardown and characterization lab in Hillsboro, Oregon. We take apart the most advanced AI and datacenter hardware, rack to transistor, and produce detailed insights on how it is built, how it compares, and why. GPUs, custom accelerators, CPUs, HBM, networking silicon, advanced packaging, every leading vendor and foundry. You will engage directly with technical experts across the industry and guide competitive analysis, design, and manufacturing decisions. This posting covers every technical role in the lab, all experience levels. Industry engagement, conference attendance, and networking are both an expectation and an opportunity. We have need and opportunity at every layer: from transistor-level process analysis to packaging and interconnects to floorplan and system architecture and integration. The stronger you deliver, the stronger your influence across the industry. One deep area is a strong application. Genuine excellence in a single area below is enough. Apply.

Requirements

Genuine exposure to leading-edge semiconductors, hardware, or systems
Reasoning from physical evidence to design and process intent
Technical writing that holds up under expert scrutiny
Hands-on aptitude for sample preparation, imaging, and analytical instruments
US work authorization preferred; sponsorship considered for exceptional candidates

Nice To Haves

Process integration, FEOL or BEOL, at leading-edge nodes
Advanced packaging: 2.5D/3D integration, hybrid bonding, high-speed interconnect
IC layout and physical design: floorplans, standard cells, P&R, custom/analog
CPU, GPU, and accelerator architecture and microarchitecture
Memory: HBM, DRAM, NAND, and their controllers
Analog/mixed-signal: SerDes, PLLs, PHYs, power management
Failure analysis and fault isolation: FIB, nanoprobing, emission microscopy
Electron microscopy and materials characterization: SEM, TEM/STEM, EDS/EELS, SIMS/XPS
Board, system, and power delivery design
Silicon bring-up, validation, and debug
Cost modeling and competitive analysis
Breadth across process, packaging, layout, architecture, and systems, every major vendor and foundry
Conference presence and standing with the industry’s technical leadership
Scope and role grow with the team and the lab
Influence over research direction, lab investments, and the teardown queue
You understand hardware from transistor to rack
You respond well to criticisms of and challenges to your technical interpretations
You already follow the industry: conferences, papers, product launches
You can tell real structure from artifact
You investigate, you ship, you close your own loops
You deliver on your responsibilities and support others in theirs; you treat everyone you work with as a peer and leave concepts of hierarchy at the door

Responsibilities

Tear down and characterize leading-edge hardware end to end: acquisition, X-ray, cross-section, delayer, imaging, interpretation
Convert physical evidence into defensible conclusions on process, packaging, design intent, architecture, and cost
Publish the complete body of work for each product: headline findings through full data and analysis
Set the analytical plan per product; operate the toolchain; direct specialized work
Track the industry through conferences, papers, patents, and your network; apply it to every interpretation
Shape lab workflows, capabilities, and equipment purchases