Silicon Performance Architect, Reality Labs

Meta•Sunnyvale, CA

1d•$178,000 - $250,000

About The Position

Reality Labs focuses on delivering Meta's vision through creating advanced AI-enabled wearables. The compute performance and power efficiency requirements of wearables require custom silicon. The custom silicon team within Reality Labs is driving the state-of-the-art forward with breakthrough work in AI, augmented reality, computer vision, machine learning, graphics, displays, and sensors. Our chips will enable wearable devices where our real and virtual world will mix and match throughout the day. We believe the only way to achieve our goals is to look at the entire stack, from transistors, through architecture, firmware, and algorithms. As an architect on the the SoC Performance team within Reality Labs, you will play a key role in leading performance modeling, correlation, workload profiling, and analysis efforts.

Requirements

Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
8+ years of experience in creating performance models using C/C++ or SystemC
Experience with SoC architecture, NoCs, memory sub-system, Quality of Service (QoS), and heterogeneous compute principles
Experience with scripting, infrastructure, automation, and visualization using Python
Experience with power concepts and trade-offs
Experience deconstructing technical problems, designing performance experiments, analyzing/visualizing data, and sharing detailed analysis in the form of documentation with peers and cross-functional partners

Nice To Haves

MS degree in EE/CS or equivalent experience
Experience working with cycle-accurate performance models and frameworks for performance architecture evaluations of various SoC components (Accelerators, NoC, DRAM, MMU, etc.)
Experience with bare-metal programming, micro-benchmarking, performance instrumentation, Simpoints, etc
Experience with RTL design verification
Demonstrated ability to integrate AI tools to optimize/redesign workflows and drive measurable impact (e.g., efficiency gains, quality improvements)

Responsibilities

Conduct thorough bottleneck analysis of existing and future SoCs to identify areas for improvement
Develop accurate models of IP components, SoC fabric, and DRAM to predict performance and inform design decisions
Analyze system usage behavior of workloads and create micro-benchmarks to evaluate performance
Identify opportunities for optimization and collaborate with hardware teams to solidify HW-SW co-design
Work across disciplines, collaborate with vendors, brainstorm ideas and solutions, develop new methodologies, and coordinate multiple initiatives