Signoff Methodology Engineer - New College Grad 2026

NVIDIA • Santa Clara, CA

4d

About The Position

NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 fueled the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI and enabled the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that matter to the world, and that only we can tackle. This is our life’s work, to amplify human imagination and intelligence, and expand what is possible. Make the choice to join us today. We are seeking an innovative Timing Methodology Engineer to help drive multi-physics sign-off strategies for the world's leading GPUs and SoCs. This position is a broad opportunity to optimize performance, yield, and reliability through increasingly comprehensive modeling, illuminating analysis, and automation. This work will influence the entire next generation computing landscape through critical contributions across NVIDIA's many product lines ranging from consumer graphics to self-driving cars and the growing domain of artificial intelligence!

Requirements

• Master's or PhD in Electrical or Computer Engineering (or equivalent experience).
• Shown problem solving skills.
• Python programming experience.
• Experience developing and maintaining automated regression tests.
• Knowledge of VLSI concepts like CMOS design, clocking, and timing of synchronous circuits.
• Understanding of mathematics/physics fundamentals of circuit design.
• Familiarity with Clocking specs: jitter, IR drop, crosstalk, spice analysis.

Nice To Haves

• Programming experience in Perl and TCL is a plus.
• Experience collaborating across multiple teams simultaneously.

Responsibilities

• Improve and validate flows for Prime-Time, Prime-Shield and Tempus STA QoR metrics for sign-off flow, and tool for high-speed designs, with focus on CAD and automation.
• Develop custom flows for validating QOR of ETM models, both of std cells and custom IPs.
• Develop flows/recommendations on STA sign-off to model deep submicron physical effects aging, self-heating, thermal impact, IR drop etc.
• Collaborate with technology leads, VLSI physical design, and timing engineers to define and deploy the most sophisticated strategies of signing off timing in design for world-class silicon performance.
• Develop tools, and methodologies to improve design performance, predictability, and silicon reliability beyond what industry standard tools can offer.
• Work on various aspects of STA, constraints, timing and power optimization.

Benefits

• Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.
• The base salary range is 116,000 USD - 189,750 USD for Level 2, and 136,000 USD - 218,500 USD for Level 3.
• You will also be eligible for equity and benefits.

What This Job Offers

• Job Type: Full-time
• Career Level: Entry Level