Signal & Power Integrity Engineer, Annapurna Labs - AI Silicon Packaging

Amazon • Cupertino, CA

1d

About The Position

Annapurna Labs (our organization within AWS) designs silicon and software that
accelerates innovation. Customers choose us to create cloud solutions that solve
challenges that were unimaginable a short time ago—even yesterday. Our custom
chips, accelerators, and software stacks enable us to take on technical
challenges that have never been seen before, and deliver results that help our
customers change the world.

We are seeking a Signal or Power Integrity Engineer to join our hardware team
and contribute to SI/PI analysis and optimization of advanced packaging
solutions for next-generation machine learning and data center ASICs.

In this role, you will support the package-level signal or power integrity
effort — performing detailed simulations, building models, and contributing to
design decisions across IC, package, and board boundaries. You'll work closely
with senior engineers to help ensure our advanced packaging technologies meet
performance, power delivery, and manufacturing targets.

Requirements

• BS degree in electrical engineering or equivalent
• 5+ years of experience in signal integrity, power integrity, or package design
• Solid understanding of either SI (S-parameter extraction, crosstalk, return loss, channel analysis) or PI (PDN impedance analysis, IR drop, decoupling strategy), with working awareness of the other
• Experience with EM simulation and SI/PI tools such as HFSS, Cadence Sigrity (PowerSI, PowerDC, Clarity), ADS, or equivalent
• Understanding of advanced packaging technologies: 2.5D/3D-IC, silicon interposers, fan-out wafer-level packaging, RDL, TSVs, and microbump interconnects
• Familiarity with stack-up design and impedance control for multi-layer organic substrates or silicon interposers.
• Good communication skills with the ability to participate in technical discussions across silicon, package, and board teams

Nice To Haves

• MS with 3+ years in signal integrity, power integrity, or package design
• Exposure to high-speed serial protocols (PCIe, UCIe, or custom SerDes) at the package level
• Experience correlating SI/PI simulations with lab measurements (TDR, VNA, oscilloscope)
• Familiarity with equalization techniques (DFE, CTLE, FFE) or PDN target impedance methodology
• Interest or experience in package co-design methodologies (chip-package-board co-simulation)
• Familiarity with high-density fan-out or silicon bridge packaging (e.g., EMIB, CoWoS, or similar)
• Exposure to package-level thermal-aware analysis, electromigration, or EMC/EMI considerations

Responsibilities

• Perform package-level SI or PI simulations for 2.5D, 3D-IC, fan-out, and silicon interposer/bridge architectures under guidance from senior engineers.
• Support package stack-up design: assist with dielectric material evaluation, impedance control analysis, layer assignment, and RDL routing studies.
• Run high-speed channel simulations (S-parameter extraction, time-domain analysis, eye diagrams) for die-to-die and die-to-board interfaces, or analyze package PDN performance (decoupling effectiveness, plane resonance, IR drop, AC impedance).
• Model advanced interconnects: microbumps, C4 bumps, TSVs, microvias, PTH vias, and RDL traces for signal or power paths.
• Build and validate models for decoupling technologies such as on-die capacitance, deep trench capacitors (DTCs), or IPD capacitors as needed.
• Coordinate with SoC die-level teams and board design teams to gather requirements and support co-optimization of package architecture.
• Flag potential package manufacturing risks - warpage, via reliability, impedance variation - and propose mitigation approaches.

Benefits

• health insurance (medical, dental, vision, prescription, Basic Life & AD&D insurance and option for Supplemental life plans, EAP, Mental Health Support, Medical Advice Line, Flexible Spending Accounts, Adoption and Surrogacy Reimbursement coverage)
• 401(k) matching
• paid time off
• parental leave

What This Job Offers

• Job Type: Full-time
• Career Level: Mid Level