Signal Integrity Engineer

Hewlett Packard Enterprise • Sunnyvale, CA

1d • Onsite

About The Position

This role has been designed as ‘’Onsite’ with an expectation that you will primarily work from an HPE office. Who We Are: Hewlett Packard Enterprise is the global edge-to-cloud company advancing the way people live and work. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today’s complex world. Our culture thrives on finding new and better ways to accelerate what’s next. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good. If you are looking to stretch and grow your career our culture will embrace you. Open up opportunities with HPE. Job Description: Work with an experienced signal integrity team with many years of experience performing high speed ASIC PAM4 SerDes and system-level signal and power Integrity analysis for cutting edge networking product design. Team members are industry experts with hands-on experience with high-speed ASIC PAM4 SerDes, channel analysis, clocking, I/O timing, on-die power integrity, system-level power integrity, CPM model and PDN optimization, PCB design for SI and PI.

Requirements

• Typically, 10 + years of Signal Integrity analysis experience with a bachelor’s degree in Electrical engineering, Computer engineering, Microwave, and/or RF engineering.
• Typically, 8 + years of Signal Integrity analysis experience with a master’s degree in Electrical engineering, Computer engineering, Microwave, and/or RF engineering.
• Experience with 56G/112G ASIC PAM4 SerDes technologies is required.
• Hands-on experience in serial channels up to 200G line rates for coefficient tuning, TP1A measurements.

Nice To Haves

• 200G ASIC PAM4 experience desired.
• Proficient with CAD tools such as Ansys HFSS, SIwave ADS, Allegro, Sigrity and MATLAB.
• Proficient with lab equipment such as oscilloscopes, Vector Network Analyzers, Time Domain Reflectometers, Spectrum Analyzers, phase noise Analyzers.
• Good lab debug skills a plus.
• Strong capabilities to debug and provide solutions for ASIC PAM4 SerDes and channel performance issues.
• Design implementation for system clocks and solid understanding of PLL design and debug.
• PCB Stack-up design using 2-d field solvers.

Responsibilities

• Perform COM (channel margin analysis) to provide design trade-offs amongst ASIC package, board, and connectors.
• Develop ASIC PAM4 SerDes channel simulation models and correlate to test structures.
• Correlate ASIC PAM4 SerDes simulation results with Measurements and work with component and ASIC vendors to improve model accuracy.
• Perform PCB timing analysis, work with board engineers and layout designers to implement all design SI rules, develop and document all layout/SI design rules and checklists.
• ASIC PAM4 SerDes parametric tuning to improve design margins of serial links.
• Perform SI DVT measurements on boards and correlate simulations with DVT measurements.
• Provide technical assessment of projects to SI management team.

Benefits

• Health & Wellbeing We strive to provide our team members and their loved ones with a comprehensive suite of benefits that supports their physical, financial and emotional wellbeing.
• Personal & Professional Development We also invest in your career because the better you are, the better we all are. We have specific programs catered to helping you reach any career goals you have — whether you want to become a knowledge expert in your field or apply your skills to another division.
• Unconditional Inclusion We are unconditionally inclusive in the way we work and celebrate individual uniqueness. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior