SerDes RTL Design Engineer

Advanced Micro Devices, Inc•Markham, ON

1d•Hybrid

About The Position

Join AMD’s SerDes Technology team to design and deliver high-performance, multi-protocol wireline transceivers in advanced CMOS processes. In this role, you will own RTL design for key digital components such as calibration loops, signal processing logic, and clock-data recovery. You will also contribute to micro-architecture planning, low-power design techniques, and performance, power, and area (PPA) optimization. This position involves close collaboration with system architects, analog designers, verification teams, and physical design engineers to achieve first-pass silicon success for AMD’s next-generation products.

Requirements

Proficient in logic design concepts and RTL coding using Verilog/SystemVerilog
Proficient in micro-architecture and developing design specifications
Proficient with design checker tools and/or functional verification tools
Knowledge of synthesis flow and static timing analysis
Knowledge of low power design and methodology
Experience in design with multiple clock domains
Experience in mixed signal design
Experience with Python, Perl, TCL and/or other scripting language
Bachelor's or master’s degree in electrical engineering, computer engineering, or related field

Nice To Haves

Experience with SerDes PHY (PMA/PCS) and/or high-speed I/O protocol is preferred

Responsibilities

Collaborate with architects to define micro-architecture for high-speed SerDes PHY.
Own RTL design for digital blocks such as calibration/adaptation loops, DSP, and CDR logic.
Apply low-power techniques and perform PPA (performance, power, area) trade-off analysis.
Develop block-level test benches and validate design functionality; support integration debug and static timing closure.
Run design checks using LINT, CDC, and RDC tools to ensure design quality.
Build behavioral models in Verilog/SystemVerilog to aid verification and system modeling.
Work closely with physical design and validation teams for tape-out sign-off and silicon bring-up.