SerDes Architect and Design Engineer

Chelsea Search Group • Austin, TX

1d

About The Position

This role involves defining the architecture, specifications, and circuit topologies for next-generation SerDes. The engineer will design high-performance analog/mixed-signal circuits in advanced node technologies, develop critical blocks like RX/TX equalization, high-speed PLLs, phase interpolators, DLLs, and TDCs. The position also includes implementing digitally assisted analog circuits, background calibration, and adaptive loops to optimize Power, Performance, and Area. Responsibilities extend to leading lab validation, debugging, and characterization of SerDes IPs, overseeing physical layout, and developing system-level modeling for link budgets and equalization strategies. Analysis of Signal Integrity and Power Integrity is also a key aspect of this role.

Requirements

• Master’s degree and/or PhD in Electrical Engineering or related fields with 10+ years of relevant experience in SerDes design
• Experience in lab bring-up, characterization, and debugging designs that reach out production
• Extensive experience with advanced node technologies (16nm/12nm, 7nm, 5nm, 3nm, 2nm processes)
• Prior experience in cross-functional interaction to deliver IP and ensuring seamless integration in SOCs
• Proven record of taking high-speed SerDes design to tape-out and volume production
• Strong communication and documentation skills

Responsibilities

• Correlate silicon measurements with simulated data, and lead performance optimization in the system environment
• Define architecture, specifications, and circuit topologies for next-generation SerDes
• Design high-performance analog/mixed-signal circuits in advanced node technologies
• Develop and overview the design of critical blocks including RX/TX equalization (CTLE, DFE), High-speed PLLs, Phase interpolators, DLLs, TDCs
• Implement digitally assisted analog circuits, background calibration, and adaptive loops to improve Power, Performance, Area
• Lead lab validation, debugging and characterization of SerDes IPs within our state-of-the-art lab
• Oversee physical layout to minimize parasitics, device stress, electromigration and process variation impacts
• Overview development of system-level modelling, with behavioral models (e.g., MATLAB, SystemVerilog, Verilog-A) to analyze link budgets, equalization strategies, and jitter budgeting
• Overview of the analysis of Signal Integrity and Power Integrity to achieve system-defined targets

What This Job Offers

• Job Type: Full-time
• Career Level: Senior
• Number of Employees: 1-10 employees