Senior Validation Engineer

Renesas Electronics•Tempe, AZ

11h•Onsite

About The Position

This position requires an experienced Engineer with a strong background in post silicon validation and characterization. The ideal candidate must have hands-on experience with silicon bring-up and validation, including high-speed analog and mixed-signal device characterization, driving debug efforts, developing test methodologies, and collaborating cross-functionally with design, system, and product engineering teams.

Requirements

Bachelor's / Master’s degree in Electrical Engineering (preferred), Computer Engineering, or a related field.
5+ years of hands-on lab experience in high-speed Analog and Mixed-signal devices.
Strong understanding of signaling levels, termination architectures, and signal integrity tradeoffs in systems.
Expertise in using typical high speed interface test equipment (BERT, High BW Oscilloscope, Signal generators and Compliance S/W, etc.).
Proficiency in scripting languages (Python) for test automation and analysis.
Excellent analytical and problem-solving skills.
Strong communication and interpersonal skills.
Strong understanding of memory interface architecture, interface protocols, standards and operation, preferably with DDR5.

Responsibilities

Perform initial silicon bring-up and debugging
Validate high speed Rx and Tx paths, PLLs including jitter analysis, eye diagram using High Bandwidth Oscilloscopes, BERT and DDR5 Application Software
Develop, execute, and automate post-silicon validation and characterization test plans of critical electrical and timing parameters for high‑speed memory buffer devices.
Collaborate closely with designers and cross‑functional partners to debug and optimize performance
Generate clear, consistent, and well‑structured report
Develop test methodologies, procedures, and assumptions to ensure results are reproducible, and accurate across validation efforts.
Support board-level debugging, signal integrity analysis