Cloud Solutions Architect Senior Timing and Clocking Characterization Engineer

The AES Group • Sunnyvale, CA

7d • Hybrid

About The Position

The AES Group is seeking a Senior Timing and Clocking Characterization Engineer to bridge analog circuit design and digital timing signoff. The role focuses on characterizing custom clocking blocks across process, voltage, and temperature (PVT) corners, developing signoff-quality timing models, and validating model behavior in block-level and full-chip timing environments. The ideal candidate has hands-on SPICE simulation and characterization expertise, along with practical experience in timing constraints, multi-mode multi-corner (MMMC) analysis, variation-aware timing, and design implementation handoff. The position is based in Mountain View, California, with an onsite or hybrid work model.

Requirements

• Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or a closely related field.
• 7+ years of relevant experience in custom circuit timing, transistor-level characterization, timing model development, or static timing analysis.
• Hands-on experience with SPICE-based characterization flows using Cadence Liberate/Liberate AMS, Synopsys PrimeLib/SiliconSmart, Synopsys NanoTime, or equivalent tools.
• Production-level STA experience with Synopsys PrimeTime or Cadence Tempus, including MMMC analysis and OCV/AOCV/POCV methodologies.
• Practical understanding of DLLs, duty-cycle correction circuits, delay lines, and custom clocking architectures.
• Strong SPICE simulation experience using HSPICE, Cadence Spectre, Synopsys PrimeSim/FineSim, or equivalent simulators.
• Proficiency in Python, Tcl, Perl, or similar languages for automation and flow development.
• Ability to analyze complex timing behavior, correlate circuit-level simulation results with timing models, and debug signoff issues.

Nice To Haves

• Experience with clocking architectures for DDR, LPDDR, HBM memory PHYs, SerDes, or die-to-die interfaces.
• Experience with FinFET or gate-all-around (GAA) process technologies and participation in at least two silicon tapeouts.
• Familiarity with physical design and implementation tools such as Cadence Innovus, Synopsys ICC2, or Fusion Compiler.
• Experience with extracted parasitic analysis and timing model correlation using StarRC, Quantus, or equivalent tools.
• Exposure to characterization and validation across extended temperature ranges, including cryogenic operating conditions.

Responsibilities

• Characterize custom and mixed-signal clocking circuits, including DLLs, duty-cycle correctors, digitally controlled delay lines, phase interpolators, and clock dividers across PVT corners.
• Generate, validate, and maintain Liberty models, including timing arcs, setup and hold checks, minimum pulse-width constraints, NLDM/CCS models, and LVF variation data as applicable.
• Evaluate propagation delay, duty-cycle distortion, jitter contributions, lock range, delay resolution, and timing sensitivities; correlate characterized models against SPICE simulation results.
• Perform block-level and full-chip STA using Synopsys PrimeTime or Cadence Tempus; debug timing violations and support timing closure across operating modes and corners.
• Create and validate SDC constraints, including generated clocks, false paths, multicycle paths, and other clock-related timing exceptions.
• Develop and maintain automated characterization, data-processing, and STA workflows using Python, Tcl, Perl, or equivalent scripting tools.
• Support implementation and signoff handoff through extracted timing models (ETMs), parasitic extraction, and correlation with physical design tools such as StarRC or Quantus.
• Collaborate with analog and custom circuit designers, digital design engineers, STA specialists, and physical design teams to resolve timing issues and improve signoff accuracy.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior