Senior Technical Staff Engineer - Validation (System Design)

Microchip•San Jose, CA

28d•$70,304 - $143,000•Onsite

About The Position

Microchip Technology Inc. is a leading provider of embedded control applications. Our product portfolio comprises general purpose and specialized 8-bit, 16-bit, and 32-bit microcontrollers, 32-bit microprocessors, field-programmable gate array (FPGA) products, a broad spectrum of high-performance linear, mixed-signal, power management, thermal management, radio frequency (RF), timing, safety, security, wired connectivity and wireless connectivity devices, as well as serial Electrically Erasable Programmable Read Only Memory (EEPROM), Serial Flash memories, Parallel Flash memories, and serial Static Random Access Memory (SRAM). We also license Flash-IP solutions that are incorporated in a broad range of products. Microchip Technology Inc. has a Senior Technical Staff Engineer - Validation (System Design) opening based in San Jose, CA. The candidate will be an expert with lab bring up and automation of FPGA design creation and validation; and be able to use FPGAs to create systems level designs; also possess expertise in development of partial re-configuration use cases. The successful candidate will be responsible for the below.

Requirements

BSEE / BSCS or equivalent with 15+ years of experience
Knowledge of FPGA architectures is a must
Possess an in-depth understanding of hardware architectures, system level IC design implementation, and knowledge of how to create end use scenarios
Strong technical background in FPGA prototype emulation, and debug
Strong technical background in silicon validation, failure analysis and debug
Excellent Board level debug capabilities in lab environment: hands-on troubleshooting skills for digital logic and analog circuit on PCB’s using oscilloscopes, digital analyzers, protocol exercisers and analyzers, integrated logic analyzers (e.g. Synopsys Identify, Xilinx Chipscope, Altera Signalscope, Lattice Reveal)
Design with RTL coding in Verilog and VHDL is a must
Experience using Simulation (ModelSim) and Synthesis (Synplicity) tools
Good knowledge of validating system level designs based on embedded processors and peripherals such as SPI, I2C, UART, Ethernet, PCI and USB
Familiarity with the bring up and on-board debug of 32Gbps SERDES
Hands-on systems level design and debug experience with following high-speed serial communications protocols (must: PHY, PCS and Data link layer of the OSI protocol stack; desirable: transaction and upper layers of the OSI protocol):
Protocol Testing at UNH for various IEEE Clauses pertaining to
Layer 1/2/3 of Gigabit Etherent
PCIe Gen3/4/5
Experience with the Lab Equipment
Spirent Test Center or equivalent Traffic Generators and Checkers
PCIe Analyzer & PCIe Exerciser
Strong commitment to quality and customer satisfaction
Excellent verbal and written communication skills in English
Able to travel 0-2 times annually if required.
C, C++ or object-oriented programming skills is required
Knowledge and experience in embedded firmware development

Nice To Haves

MSEE / MSCS preferred
Knowledge and experience in JTAG, SVF and 1532 standards and STAPL programming is desirable
Experience with Python/PERL/TCL scripting
Familiarity with any high speed SERDES controllers that make use of 32Gbps PCS, PMA :
Ethernet 1, 2.5, 5, 10, 25, 40, 50, 100, 200, 400 Gbps, including familiarity with (U)S(X)GMII
Interlaken (4.25 to 412.5 Gbps)
OTN OTUx (2.66 to 131 Gbps), or SONET/SDH OC3/12/48/192
(E,X,XGS,NG)-PON or 100G-EPON
Video interfaces SDI-SD/HD/3GHD and SDI (5.94, 11.88Gbps), Displayport (6.48 to 25.92Gbps), HDMI (3.96 to 42.66 Gbps)
JESD204C (6.375 to 32 Gbps)
Design and debug experience for any of the below high-speed serial communications protocols is a plus, but not necessary:
Hybrid Memory Cube
CPRI Rate 1 to 10+
Serial Rapid IO 4.1
USB 3.0
SATA I, II, III
Fiber Channel
CoaXpress

Responsibilities

Be an expert with use of FPGAs to create systems level designs to bring up and debug such systems in the lab, including having deep experience in validating systems level UCs for partial reconfiguration
Architecture definition and FPGA design creation utilizing all hardware features and IP cores targeted to existing and future Microchip products.
System and FPGA design must exercise all the use models targeted for each product mimicking end applications in a customer setting.
Develop high level system and product level validation plans for new and existing silicon products and project, execute per plan. Review dependencies, estimate effort and identify and communicate risk.
Understand hardware architectures, define use models and execute / oversee system level design implementations required to utilize the silicon features.
Be not only an effective contributor but also the technical expert related to protocols using high speed serial interfaces in a cross-functional team-oriented environment.
Write high quality code in Verilog, VHDL and C code. Maintain existing code. Support regression and re-use.
Learn new system designs and validation methodologies. Understand FPGA architectures.
Act as the authoritative expert in knowledge domain area(s), be able to mentor senior and junior engineers and provide technical guidance. This involves assigning and monitoring tasks of employees and contractors.
Collaborate with cross-functional managers/teams to identify and resolve inter-dependencies.
Define and improve process followed in the department; follow quality metrics and assess per project.
Must be willing to take regular late night or early morning calls to interface with the engineering team in India Standard Time zone, when and if required.
Use AI based tools to automate workflows and help improve the FPGA design and validation processes