Senior Technical Program Manager – Silicon Co-design

NVIDIA•Austin, TX

9d•$168,000 - $322,000•Hybrid

About The Position

NVIDIA’s Silicon Co-Design Group sits at the intersection of architecture, silicon, systems, and manufacturing — where engineering judgment at the highest level drives real-world product outcomes at scale. This is not a coordination role. It is an ownership role. We are looking for a Senior TPM who has left a visible mark on programs: someone whose decisions changed schedules, prevented crises, and made the next program run better. You have owned SoC programs from architecture through tape-out, carried ambiguous multi-team problems to closure, and created methods or tools others adopted. You spot integration risk before it becomes a program event. You make trade-offs that engineers respect. You improve the system after every program, not just report on it. The exceptional hire also uses AI deliberately, not as a credential, but as a force multiplier with demonstrated workflow impact.

Requirements

Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field (or equivalent experience); a master’s is a plus.
10+ years in technical roles, with at least 5 years in technical program management owning SoC programs from architecture through tape-out.
Deep, hands-on understanding of SoC design cycles, verification, and productization — you know the stages, what each involves, and what fails and why.
Demonstrated ability to work across the silicon–system–software boundary: enough depth to spot integration risks and drive resolution without having to be the expert on every question.
Proven track record running fast development cycles under uncertainty — you generate transparency rather than wait for it.
The uses AI deliberately not as a credential, but as a force multiplier with demonstrated workflow impact.
Communication that is precise, direct, and right-sized for the audience.

Nice To Haves

You have used AI-powered program management tools in production — automated status, risk flagging, dependency tracking — and can tell specifically which tools improved outcomes versus added noise.
You have worked with AI/ML teams on inference infrastructure and aligned multi-functional delivery to go-to-market timing for AI-accelerated products.
You have evaluated and rolled out AI productivity tools (coding assistants, automated documentation) and can make a concrete, evidence-backed case for what actually improved engineering velocity.

Responsibilities

Define and drive schedules, surface dependencies before they block work, and own multi-functional alignment from architecture review through tape-out.
Accountable for delivery, not only oversight.
Participate in critical design reviews, flag scope and integration risks early, and make trade-off calls others depend on — schedule vs. quality, coverage vs. velocity, design change vs. firmware workaround.
Act as the primary technical link across silicon, systems, software, operations, and marketing.
Catch misalignments before they hurt the program; drive fixes without requiring deep expertise across every domain.
Identify technical and schedule risks early, build mitigations with engineering, and move work forward with clarity and context.
Capture lessons from completed programs and put in place changes that measurably improve speed, quality, and predictability — not just documentation of what happened.