Senior Staff Test Engineer

Credo•San Jose, CA

1d•$160,000 - $220,000

About The Position

The Senior Staff Test Engineer will be responsible for leading hardware development for our next generation DSP and SerDes products. This role ensures hardware is functional, reliable, and manufacturable by systematically identifying and preventing failures—and requires deep technical expertise, strategic foresight, and cross-functional collaboration. The engineer will also play a key role in mentoring and upskilling teams across Product, CP/ATE/SLT, and Operations Engineering.

Requirements

Bachelor’s Degree in Electrical Engineering or Computer Science/Software Engineering or equivalent is required.
10+ years of meaningful experience.
In depth knowledge of Semiconductor Manufacturing Process.
Proven experience in developments for Automatic Test Equipment (ATE).
Deep understanding of RF and Analog Fundamental, Design for Test and Manufacturing Concepts.
Expertise in Semiconductor Test Methodology.
Experience working on Digital, Mixed Signal, RF/SOC, & PMIC Devices with hands on VLSI ATE experience.
Strong knowledge of hardware design methodology.
Strong knowledge of hardware design tools such as CAD, Allegro, and etc.
Excellent interpersonal skills to work with internal team members and external suppliers to drive project execution.
You should be a standout colleague, work well independently as well as collaboratively in a team setting.

Nice To Haves

Master’s Degree preferred.
System level experience is a plus.

Responsibilities

Develop, debug, and maintain ATE test programs for production, characterization, and qual on Advantest 93K test platform.
Perform pattern processing and conversion from design environments into tester-compatible formats.
Execute silicon characterization and validation across process, voltage, and temperature corners; analyze results to drive yield and performance improvements.
Work with DFT, design, and product engineering teams to define test requirements, improve test coverage, and close gaps.
Optimize test flows and methodologies to reduce overall test time and cost while ensuring high quality.
Drive correlation between simulation, bench, and tester environments.
Support high-volume manufacturing ramps, addressing test escapes, yield excursions, and test program robustness.