Senior Staff Software/Firmware Engineer-RISC-V validation backbone - spanning MCU integration, firmware, and automation

Marvell Technology•Santa Clara, CA

14d•$131,010 - $196,300

About The Position

Marvell Central Engineering (CE) develops Marvell most advanced High-Speed SerDes (HSS) IPs covering multiple applications, Switch, Automotive, Storage, Optics, etc. Acting as the engine to the company, Central Engineering provides the source of power to every business unit in Marvell system. Central System Engineering (CSE) in Central Engineering, independent of other CE functions including DSP algorithm development, circuit design, physical design, packaging, etc., is a function team responsible of validating all Marvell HSS IPs in the lab environment and supporting all Marvell business units for fast and smooth SoC production.

Requirements

8+ years of experience in embedded systems, firmware, or SoC development
Strong proficiency in C/C++ with bare-metal programming
Experience with low-level system development: Boot flows, startup code, linker scripts
Memory-mapped I/O and register-level programming
Interrupt handling and real-time constraints
Hands-on experience debugging HW/SW integration issues (silicon, FPGA, or RTL simulation)
Solid understanding of computer architecture fundamentals (CPU, memory hierarchy, buses)

Nice To Haves

Experience with RISC-V systems or similar MCU architectures (e.g., ARM Cortex-M)
Exposure to embedded SoC integration (bus fabrics such as AHB/AXI-lite)
Familiarity with interrupt systems such as PLIC and CLINT
Experience with PHY / SerDes / high-speed IP bring-up or validation
RTOS experience (e.g., FreeRTOS, Zephyr)
Exposure to silicon bring-up or post-silicon validation
Experience building firmware-driven validation frameworks or automation infrastructure
Familiarity with simulation/emulation workflows (RTL co-sim, FPGA prototyping)
Experience in closed-loop control systems (calibration, tuning, adaptive algorithms)
Exposure to hardware verification or validation environments (UVM, testbenches)

Responsibilities

Lead integration of an embedded RISC-V core (e.g., SiFive E24 Core) into chip validation environments
Define MCU subsystem architecture: memory map, boot flow, and execution environment
Integrate and validate system interconnect (AHB/AXI-lite) and memory hierarchy (ROM/SRAM)
Implement interrupt architecture using PLIC and CLINT
Develop bare-metal and RTOS-based firmware for PHY/IP control and bring-up
Implement calibration, training, and tuning algorithms for high-speed interfaces
Build reusable firmware frameworks for: Register-level control abstraction, Test sequencing and automation, Logging, diagnostics, and error handling
Lead silicon and pre-silicon bring-up using embedded firmware
Debug cross-domain issues across hardware, firmware, and PHY behavior
Enable rapid iteration of initialization, configuration, and recovery flows
Drive root-cause analysis for system-level failures
Integrate RISC-V firmware into existing PHY validation automation framework
Enable unified validation across simulation, emulation/FPGA, and silicon
Develop firmware-driven test scenarios replacing or complementing external stimulus
Build infrastructure for automated test execution and result collection
Transition validation methodology from directed external tests to software-driven closed-loop validation
Define and implement coverage for: Functional PHY behavior, Corner cases and stress conditions, Recovery and error handling scenarios
Ensure reusability of validation content across programs and platforms
Partner with RTL teams on SoC integration and interface definitions
Work with validation teams to align firmware-driven test strategies
Collaborate with architecture teams to define scalable validation platform direction
Support system-level debug across hardware/software boundaries
Maintain RISC-V toolchain environment (GCC, linker scripts, startup code)
Support debug infrastructure (JTAG, OpenOCD, GDB workflows)
Drive automation for firmware build, deployment, and regression execution