About The Position

In this role, you will help shape AI/ML hardware acceleration by driving TPU technology that powers demanding AI/ML applications. You will contribute to custom silicon solutions and apply design and verification expertise to complex digital designs, with a focus on TPU architecture and integration into AI/ML-driven systems. You will work at the intersection of AI research and infrastructure engineering, defining long-term goals and architectural roadmaps for machine learning training and serving. The role leads the integration of foundational ML research with advanced architectures to deliver high-performance, power-efficient accelerators. Google’s AI and Infrastructure team delivers AI and infrastructure capabilities at scale, efficiency, reliability, and velocity for Google employees, Cloud customers, and users worldwide. Its work spans software and hardware, including TPUs, Vertex AI for Google Cloud, global networking, data center operations, and systems research.

Requirements

  • Bachelor’s degree in Computer Science, Computer Engineering, Electrical Engineering, a related technical field, or equivalent practical experience.
  • 8 years of experience in software development, systems engineering, or hardware/software co-design.
  • 5 years of experience with machine learning systems, architecture, performance modeling, or simulation frameworks.
  • Experience with ML frameworks such as JAX, PyTorch, or TensorFlow, and with large language model inference or training workloads.

Nice To Haves

  • Master’s degree or PhD in Engineering, Computer Science, or a related technical field.
  • 5 years of experience in a technical leadership role leading project teams and setting technical direction.
  • Experience driving multi-generational hardware/software co-design or performance optimizations for massive-scale ML inference and training.
  • Experience with accelerator programming, ML compilers, and deep learning execution models.
  • Experience analyzing system-level performance across compute, memory, interconnects, and packaging trajectories.

Responsibilities

  • Lead the technical goals, roadmap, and software architecture for hardware/software co-design, optimizing large-scale ML inference and training systems.
  • Design, develop, and oversee simulation frameworks, cycle-accurate performance models, and system analysis tools to evaluate architectural trade-offs.
  • Architect scalable software solutions, kernels, and execution pipelines that bridge frontier ML model architectures with next-generation custom silicon accelerators.
  • Drive system-level performance optimization across distributed ML infrastructure, balancing compute, memory bandwidth, and inter-chip networking requirements.
  • Provide technical leadership and mentorship across hardware, compiler, and ML research teams to align on goals and transition co-design innovations into production.

Benefits

  • 25% bonus target
  • Equity
  • Benefits
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