Senior Staff Product Application Engineer-Memory Subsystems

Advanced Micro Devices, Inc•San Jose, CA

About The Position

Join our team to drive customer success on the memory subsystem across our silicon portfolio, covering DDR and LPDDR across generations and the memory controller, Network-on-Chip and physical interface behind them. You will be a technical point of contact for escalated memory cases, from early design-in and bring-up through production support. You are the person strategic customers escalate to when memory does not behave the way the specification says it should. You will root-cause those failures on real systems, drive the fix through the teams that own it, and review next-generation memory architecture and design to catch defects before they reach silicon. You will also own the memory documentation customers design against. The scope runs from JEDEC device behavior and PCB routing, through controller architecture and RAS features, to the product and roadmap decisions your findings should drive.

Requirements

Extensive hands-on experience with memory subsystems in an applications, architecture, design, or validation role, built across multiple DRAM generations and product cycles.
Expertise across DDR and LPDDR generations (DDR4/DDR5, LPDDR4/4X/5/5X/6), with fluency in the relevant JEDEC specifications and in module variants (UDIMM, SODIMM, RDIMM, LRDIMM, CUDIMM).
Excellent technical writing, with a track record of authoring and publishing customer-facing documentation that an external audience designs against: product guides, user guides, datasheets, answer records and tutorials.
Deep knowledge of DRAM, memory controller and PHY architecture: command scheduling and arbitration, address mapping and decode, calibration and training, DQS gating and delay-line behavior, termination and drive strength, voltage and temperature tracking, and page policy, with experience evaluating and validating RAS features.
Working knowledge of on-chip interconnect architecture, including Network-on-Chip, and of bandwidth and latency budgeting.
Proven root cause of system-level memory failures, attributing each correctly across the DRAM device, board, controller IP, firmware, tools and silicon, including reading calibration and training firmware closely enough to trace a failure to the step that produced it.
Hands-on lab debug with oscilloscopes, signal generators, BERTs, logic and protocol analyzers, and register-level debug over JTAG.
Hands-on DRAM SI/PI and timing analysis (measurement on real hardware, eye and margin analysis, and channel simulation with IBIS and IBIS-AMI models) together with a practical understanding of PCB layout and routing for DDR/LPDDR.
Experience working directly with strategic customers in technical or architecture-facing roles, translating system-level challenges into product or roadmap decisions, and influencing multi-functional teams without direct authority, with a track record of mentoring and running technical reviews.
Demonstrated use of AI in engineering workflows, applying AI/LLM/ML tools to identify design gaps, summarize collected data for distribution and analysis, and drive productivity in debug, automation and documentation.
Strong C for writing targeted memory test applications, and able to read architecture specifications, design documentation and SystemVerilog/Verilog RTL closely enough to identify implementation bugs.

Nice To Haves

HBM experience is a plus.
Platform-level signal and power integrity is a plus.

Responsibilities

Own escalated customer support issues for memory, from early design-in and bring-up through production support.
Partner with key customers to root-cause system memory failures such as intermittent errors, calibration and training failures, and margin and boot issues.
Attribute each correctly across DRAM, board, controller IP, calibration firmware and silicon, and drive the fix to closure.
Be the authority on DDR and LPDDR, covering JEDEC standards, device behavior, module topologies, ranks, widths and supported data rates.
Know how traffic reaches the controller across the Network-on-Chip, including QoS, arbitration, and bandwidth and latency budgeting.
Author the customer-facing memory documentation, including product guides, user guides, datasheets, answer records, tutorials and layout guidance, and publish resolutions internally and externally.
Review memory and NoC architecture and design specifications for next-generation silicon, identifying gaps, inconsistencies and design bugs, and proposing fixes.
Evaluate and validate its memory RAS features.
Perform DRAM SI/PI and timing measurements.
Apply PCB layout and routing knowledge for DDR and LPDDR to assess customer designs and define the layout guidance we publish.
Support IBIS/IBIS-AMI models and channel simulation.
Create experiments and tooling that catch memory health issues before they are reported.
Write targeted memory tests in C to stress and characterize specific failure modes on real hardware.
Translate system-level challenges into product and roadmap decisions on supported configurations, data rates, feature scope and documentation accuracy.
Drive teams across IP, firmware, tools, signal integrity, validation and quality without direct authority, for feature enablement, optimization and characterization.
Use AI/LLM/ML tools to surface design gaps, summarize and correlate large test and log datasets, and drive productivity in debug, automation and documentation.