Senior Staff Mixed Signal Verification Engineer

Renesas Electronics•Chandler, AZ

13d•Onsite

About The Position

As a Mixed-Signal Verification Engineer, you will be responsible for the verification and modeling of mixed-signal power management devices, including PMICs, battery chargers, switching regulators, and related analog IP. You will work closely with design, systems, verification, CAD, and customer teams to drive successful development, integration, and sign-off of complex mixed-signal power chips.

Requirements

B.S. or M.S. in Electrical Engineering, Computer Engineering, or a related field.
8-12+ years of experience in mixed-signal verification, AMS/DMS simulation, behavioral modeling, power management IC development, or related semiconductor design activities.
Strong experience with switching regulators, battery chargers, PMICs, SystemVerilog, Verilog-AMS, UVM, Cadence Xcelium, Spectre, and mixed-signal verification sign-off methodologies is highly desirable.
Experience developing behavioral models and debugging complex analog-digital interactions is a plus.
Strong communication, teamwork, and customer-facing skills, with the ability to effectively collaborate across cross-functional engineering teams and present technical information to both internal and external stakeholders.

Responsibilities

Lead chip-level verification of analog and mixed-signal circuits using AMS and DMS methodologies, integrating analog behavioral models with digital RTL and UVM-based environments.
Develop verification strategies, drive coverage closure, and support product tapeout milestones.
Create, maintain, and validate behavioral models using SystemVerilog RNM and Verilog-AMS, translating circuit and system requirements into high-performance models suitable for both AMS co-simulation and full-chip DMS verification.
Ensure model accuracy through correlation against specifications and schematic references across operating conditions.
Develop and execute comprehensive verification and modeling plans with full traceability from design requirements through coverage closure and tapeout sign-off.
Track verification readiness and proactively identify risks to product schedules.
Own debug and root-cause analysis of mixed-signal verification issues, including failing test cases, model inaccuracies, analog-digital interface problems, convergence issues, and simulation performance bottlenecks.
Drive resolution across design, modeling, and verification teams.
Partner with analog and digital designers, system architects, verification engineers, and CAD teams to improve modeling accuracy, simulation efficiency, and verification quality.
Participate in architecture and design reviews, influencing design decisions to improve verification effectiveness and reduce project risk.
Participate in design reviews to evaluate circuit topology and design partitioning from a verification and modeling perspective, recommending architectural choices that simplify behavioral modeling, improve simulation convergence, and reduce verification risk.
Support silicon validation and root-cause analysis of complex system-level issues by correlating simulation predictions to bench measurements.
Document verification plans, model validation methodologies, coverage results, and sign-off metrics to ensure clear communication and traceability throughout the product lifecycle.
Interface directly with external customers to present verification status, review coverage results, address technical questions, and ensure verification deliverables meet product and customer requirements.