Senior Staff Integration EngineerSr Staff Engineer

Seagate Technology • Bloomington, MN

7d • Onsite

About The Position

At Seagate our mission is to build the world’s best data storage devices.

The Advanced Transducer Development group is a global R&D organization that develops new recording head technologies to advance areal density and enable Seagate’s HDD (Hard Disk Drive) 4 year+ product roadmap. Our process team uses state-of-the-art wafer fabrication tools and cleanroom facilities to innovate and deliver leading-edge writers and read sensors.  With an emphasis on proving feasibility of new devices, processes and materials, we help build Seagate’s future time-to-market leadership.

If you are excited by innovative technology development, are naturally creative, and passionate about seeing ideas come to life then this could be a perfect fit for your research and development career.About the role - you will:
Lead the wafer fabrication of advanced head devices from concept through component-level feasibility demonstration.
Work with the design team to translate device concepts into feasible, predictive test structures.
Lay out wafer build plans, including CAD, process module, test requirements, and success criteria.
Coordinate the work of unit process owners (deposition, litho, etch, CMP, wet process) to achieve equipment and process readiness for prototype wafer builds.
Manage wafer supply for critical experiments through wafer starts, daily WIP decisions and ownership of daily velocity and moves parametrics.
Ensure built devices meet design intent for geometry, performance, and reliability.
Detect, pareto and solve new defect modes related to new process module integration.
Explore new process techniques to define hardware paths needed for advanced capability and manufacturability.
Manage experiments, projects and wafer tracking to deliver results to the designated schedule.
Participate in transfers or promising new technologies to the product development engineering team.
Contribute to Seagate’s IP portfolio in the form of invention disclosures, patents, trade secrets, peer-reviewed journal articles, and/or white papers.
About you:
You are self-motivated, intellectually curious, adept at problem solving, and have a strong attention to detail.
You are an honest and respectful team player, capable of working in strong partnership with a diverse global group of engineers and technicians.
You are a well-organized multitasker, able to maintain focus on day-to-day wafer processing needs but also keep a cadence of longer-term development work.
You are interested in and able to provide leadership through early-stage growth of a young but talented engineering team.
You maintain thorough documentation of results and can clearly present and discuss them with other staff members in engineering and management forums.
You have a track record of innovation and problem-solving, and regularly use external resources (vendors, conferences, literature) to inspire new ideas and directions.
You are able and eager to work in a mix of clean room and laboratory environments.

Requirements

• Bachelor's Degree in Materials Science, Electrical Engineering, Physics, Applied Physics, Chemistry or related science and 12+ years of experience, or Master’s degree in Materials Science, Electrical Engineering, Physics, Applied Physics, Chemistry or related science and 8+ years of experience, or PHD and 5+ years of experience or equivalent education and experience.
• Strong hands-on experience and in-depth understanding of wafer device builds in clean room or industrial wafer fab environments.
• Experience in device building, including CAD layout, device build flow simulation/visualization, WIP management and wafer-scale integration of new processes.
• Broad knowledge of conventional wafer unit processes (litho, deposition, etch, CMP, wet process) and prior device or process module ownership experience.
• Facility with a broad set of in-room characterization techniques including sheet film and device-level measurements (e.g. AFM, ellipsometry, 4pt probe, XRF, FIB, SEM, (S)TEM, etc).
• Knowledge of standard statistical experimentation methods including hypothesis testing, DOE design and analysis and ANOVA.  Familiarity with JMP or R preferred but not essential.

Responsibilities

• Lead the wafer fabrication of advanced head devices from concept through component-level feasibility demonstration.
• Work with the design team to translate device concepts into feasible, predictive test structures.
• Lay out wafer build plans, including CAD, process module, test requirements, and success criteria.
• Coordinate the work of unit process owners (deposition, litho, etch, CMP, wet process) to achieve equipment and process readiness for prototype wafer builds.
• Manage wafer supply for critical experiments through wafer starts, daily WIP decisions and ownership of daily velocity and moves parametrics.
• Ensure built devices meet design intent for geometry, performance, and reliability.
• Detect, pareto and solve new defect modes related to new process module integration.
• Explore new process techniques to define hardware paths needed for advanced capability and manufacturability.
• Manage experiments, projects and wafer tracking to deliver results to the designated schedule.
• Participate in transfers or promising new technologies to the product development engineering team.
• Contribute to Seagate’s IP portfolio in the form of invention disclosures, patents, trade secrets, peer-reviewed journal articles, and/or white papers.

Benefits

• eligibility to participate in discretionary bonus program
• medical, dental, vision, and life insurance, short-and long-term disability, 401(k), employee stock purchase plan, health savings account, dependent care, and healthcare spending accounts
• paid time off, including 12 holidays, flexible time off provided pursuant to Seagate policy, a minimum of 48 hours of paid sick leave, and 16 weeks of paid parental leave

What This Job Offers

• Job Type: Full-time
• Career Level: Senior