Senior Staff Engineer, Memory/SRAM Circuit Design Engineer

Samsung•San Jose, CA

36d•Onsite

About The Position

Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL) are building a center of excellence for Intellectual Property (IP) applied to high-performance computing devices. As a Senior Staff Memory/SRAM Circuit Design Engineer, you will drive the development of high-performance, power- and area-efficient SRAM and custom memory macros for next-generation CPU and GPU applications. Your work will influence product competitiveness by delivering differentiated memory solutions optimized for advanced technology nodes. This individual contributor role is part of a specialized custom design team driving innovation in circuit design and design-technology co-optimization (DTCO). You will translate advanced process capabilities into robust, production-ready memory solutions, influencing circuit architecture and technology direction to achieve industry-leading performance, power, and area (PPA) targets. You will contribute to the end-to-end design and delivery of SRAM and custom memory circuits, including transistor-level design, logic and functional verification, timing generation, layout supervision, physical verification (LVS/DRC), and post-layout validation (SPICE, EMIR/noise). You will develop and apply advanced circuit design techniques, explore new architectures and methodologies to optimize PPA targets beyond standard memory solutions. You will lead DTCO-driven innovation by analyzing the interaction between process technology and circuit behavior, and influencing layout rules, device characteristics, and memory architecture for advanced nodes (≤5nm) to the process technology team. You will drive cross-functional collaboration with hardware design, architecture, SoC, software, and foundry teams to enable seamless integration of SRAM into system designs, while contributing to methodology, automation, and flow improvements. You will inspire high performance by mentoring junior engineers, fostering a culture of ownership and innovation, documenting designs and methodologies, and staying ahead of emerging memory technologies and advanced technology nodes.

Requirements

11+ years of experience with a Bachelor’s Degree in Computer Science/Engineering, or 9+ years of experience with a Master’s Degree, or 7+ years of experience with a Ph.D.
Strong expertise in SRAM circuit design, timing generation, logic/functional verification, and physical verification (LVS/DRC).
Experience with advanced node design and DTCO, including technology, logic and memory cell architecture, and interconnect exploration, for below 5nm.
Strong proficiency with industry-standard design tools and scripting languages (Python, Perl).
Strong understanding of computer architecture and SoC integration.
Excellent analytical, and problem-solving skills, with the ability to propose data-driven solutions and guide execution.
Excellent written and verbal communication skills for documenting designs, methodologies, and best practices.
Excellent collaboration skills, with the ability to navigate ambiguity and influence in a fast-paced, global team environment.

Nice To Haves

Multiple-Foundry experience is a big plus.
Ability to design memory with excellent PPA (Power, Performance, Area) under given SPEC.
Lead of memory bit cell and custom circuit related DTCO.
Exposure to emerging technologies such as Processing-in-Memory (PIM).

Responsibilities

Drive the development of high-performance, power- and area-efficient SRAM and custom memory macros.
Translate advanced process capabilities into robust, production-ready memory solutions.
Influence circuit architecture and technology direction to achieve industry-leading PPA targets.
Contribute to the end-to-end design and delivery of SRAM and custom memory circuits.
Develop and apply advanced circuit design techniques, exploring new architectures and methodologies.
Lead DTCO-driven innovation by analyzing process technology and circuit behavior interactions.
Influence layout rules, device characteristics, and memory architecture for advanced nodes.
Drive cross-functional collaboration with hardware design, architecture, SoC, software, and foundry teams.
Contribute to methodology, automation, and flow improvements.
Mentor junior engineers, foster a culture of ownership and innovation, and document designs and methodologies.
Stay ahead of emerging memory technologies and advanced technology nodes.