Senior Staff Engineer, Digital IC Design

Marvell Technology•Santa Clara, CA

2d•$134,390 - $201,300

About The Position

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. The Custom Compute, Storage and Automotive Business Unit provides custom solutions for high performance compute, server, network processing, storage and Automotive applications. CCS&A products employ state-of-the-art custom and industry standard technologies such as CXL, PCIE, Ethernet, and ARM CPU cores.

Requirements

Bachelor’s degree in Computer Engineering, Electrical Engineering or related fields and 5+ years of related professional experience. Or Master’s degree and/or PhD in Computer Engineering, Electrical Engineering or related fields with 3+ years of experience.
Proven experience in taping out complex SoCs and post silicon debug
Strong RTL design skills in SystemVerilog
Hands-on experience with SoC integration and debug, along with clock/reset design, CDC, and timing constraints.
Understanding of how front-end RTL decisions impact physical implementation and verification.
Familiarity with industry standard ARM protocols (Ex: APB, AHB, AXI, CHI) and SoC interconnect (NOC) architectures.
Excellent communication skills and ability to participate in problem-solving and quality improvement activities.
Demonstrates good analytical and problem-solving skills.
Experience with scripting languages, e.g., Python or Tcl

Responsibilities

Work with SOC Integration team to integrate internal and external IP blocks at the chip level.
Take ownership of a portion of an SOC design and drive it from initial stages to completion
Collaborate on floorplan
Responsibility for interconnection of IP blocks
Static checks
Assist with subsystem and chip level verification efforts
Drive to timing closure
Collaborate with cross-disciplinary team including architecture, physical design, chip and block level verification, Design for Test, and packaging to meet all requirements to tape-out a high quality, zero-defect product.
Use both industry and internal EDA tools to run functional simulations, gate-level simulations, code quality checks, and CDC at the chip level.
Lead design effort for internally developed processor IP blocks to meet specific architectural needs.
Work closely with verification and implementation teams to meet product requirements.
Deliver micro-architectural specifications for these designs.
Utilize and participate in the development of automation tools to accelerate the pace of development.
Leverage next-generation AI tools to enhance existing work flows.