Senior Staff Engineer, Design Verification
Marvell Technology•Santa Clara, CA
•$134,390 - $201,300
About The Position
As a SoC-level design verification engineer, you will be responsible for the development and maintenance of UVM testbench components and other verification testing collaterals. You will be a member of a team charged with ensuring design quality in a variety of complex SoC architectures.
Requirements
- Bachelor’s degree in Computer Engineering, Electrical Engineering or related fields and 5+ years of related professional experience. Or Master’s degree and/or PhD in Computer Engineering, Electrical Engineering or related fields with 3+ years of experience.
- Experience in developing complex/random verification environment components using System Verilog/UVM
- Experience with writing and executing detailed verification test-plan.
- Experience with verification tools, as well as bug tracking and regression mechanisms.
- Excellent communication skills and ability to participate in problem-solving and quality improvement activities.
- Demonstrates good analytical and problem-solving skills.
- Basic proficiency with C/C++.
- Experience with scripting languages, e.g., Python or Perl
- Working knowledge of the Linux operating system
Responsibilities
- Analyze architectures and designs to create comprehensive test plans and strategies.
- Contribute to the development of verification environments.
- Develop tests/testing strategies to achieve coverage goals.
- Debug failures and work with designers to resolve issues.
- Mentoring and guiding junior engineers
Benefits
- employee stock purchase plan with a 2-year look back
- family support programs
- robust mental health resources
- recognition and service awards
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What This Job Offers
Job Type
Full-time
Career Level
Senior
