Senior Staff Design Verification Engineer

Renesas Electronics•Duluth, GA

5d•Onsite

About The Position

Renesas is looking for a highly experienced Senior Staff Design Verification Engineer to provide technical leadership for the verification of leading-edge memory interface products for data center, AI, and cloud computing applications. This role will help drive verification strategy and execution for advanced memory data buffer products, including DDR6 and future generations. The ideal candidate is a recognized technical expert with deep semiconductor design verification experience using SystemVerilog and UVM. Previous DDR or memory experience is an advantage, but is not required.

Requirements

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field, or equivalent experience.
10+ years of related experience in semiconductor design verification
Deep experience in semiconductor design verification, including technical leadership of complex verification efforts.
Advanced proficiency with SystemVerilog and extensive hands-on experience with UVM (Universal Verification Methodology).
Experience defining verification strategies and developing verification plans from product and design specifications.
Strong experience developing, optimizing, and debugging UVM-based verification environments and testbenches.
Strong experience with functional verification, coverage, checkers, test development, debugging, and coverage closure.
Demonstrated ability to independently resolve complex technical problems and make verification methodology decisions.
Demonstrated ability to provide technical guidance and mentorship to other engineers

Nice To Haves

Experience with DDR4, DDR5, memory interfaces, data buffers, or other high-speed memory technologies.
Experience leading verification efforts across multiple blocks, features, or engineering groups.
Experience developing verification methodologies or best practices with applicability beyond an individual project.

Responsibilities

Provide technical leadership for verification of complex semiconductor designs at the block and system level.
Define and drive verification strategies, methodologies, test plans, and coverage approaches for complex designs and features.
Lead the development and optimization of SystemVerilog/UVM verification environments and testbenches.
Drive verification execution, functional coverage, debugging, and coverage closure.
Take ownership of significant verification efforts and make independent technical decisions regarding verification methods, techniques, and priorities.
Work closely with design engineers and other technical stakeholders to ensure designs meet functional and performance requirements and are effectively verifiable.
Analyze complex verification and design issues, determine root causes, and drive solutions.
Anticipate technical challenges and identify improvements to verification methodologies, processes, quality, and efficiency.
Drive the development of reusable verification solutions, methodologies, and best practices that can benefit broader engineering efforts.
Participate in and provide technical leadership during architecture, feasibility, design, and technical reviews.
Serve as a subject matter expert in design verification and provide technical guidance on complex problems.
Mentor and provide guidance to verification engineers across projects and experience levels.
Coordinate with technical stakeholders across teams and disciplines to achieve verification milestones and objectives.
Communicate verification status, technical risks, recommendations, and readiness to engineering leadership and project stakeholders.