Senior Staff Design Engineer, IC Layout

Impinj

10h•$158,700 - $238,100•Hybrid

About The Position

Impinj is a leading RAIN RFID provider and Internet of Things pioneer. We’re inventing ways to connect every thing to the Internet — including retail apparel, retail general merchandise, healthcare items, automobile parts, airline baggage, food and much more. With more than 100 billion items connected to date, and multiple Fortune 500 enterprises around the world using our platform, we solve for a better understanding of our world. If it’s a thing, we’re working to connect it. Join Impinj and help us realize our vision of a boundless IoT— connecting trillions of everyday items to the Internet. Team Overview: The Layout Design Engineering group is an integral part of the Silicon Engineering department, working closely with the analog RFID end-point IC development team and the Reader IC team, internationally. The team is responsible for delivering tape-outs for RFID products, test chips, reader ICs, and DOEs (design of experiments) work that sits at the center of how Impinj brings new silicon to market. Layout decisions made by this team directly influence the power efficiency, cost, and time-to-market of every piece of silicon we ship, making the group's work foundational to Impinj's mission. The team operates with a continuous-improvement mindset, adapting quickly and challenging each other to remain best-in-class in both quality and speed, with meticulous attention to detail to ensure designs have long-term reliability and zero defects, at production volumes in the many billions and eventually trillions of tags per year.

Requirements

Bachelor’s or master’s degree in computer or electrical engineering or a related technical field, with 12+ years of experience
Experience in custom analog, RF, and mixed-signal layout, with ability to lead complex ICs from conception to tapeout
Versed in tapeout flows with experience in final database preparation and tapeout checklists
Ability to lead and mentor other layout engineers as the top-level floorplan/IC integration owner, partnering with circuit designers to resolve complex problems
Expert in full-chip/SOC-level floorplanning and integration — physical implementation of cells and analog blocks/IPs, pin-ring generation, routing management, and full-wafer assembly — with experience delivering advanced floorplan strategies and debugging DRC/LVS verification across intermediate hierarchies and at the full-chip level, for both analog-on-top (AOT) and digital-on-top (DOT) methodologies
Understanding of semiconductor manufacturing processes and foundry technologies across advanced process nodes down to 16nm for ultra-low-power and high-fidelity applications
Understanding of analog layout challenges and layout-dependent effects in advanced processes — noise coupling, matching, parasitics, LOD, WPE, PSE, and coloring — along with proficiency in mitigation techniques such as guard rings, DNW, PN junctions, parasitic management, signal integrity, reliability (EMIR), and ESD.
Expert knowledge of Cadence Virtuoso schematic and layout editors, plus Cadence/Siemens layout verification tools (including PVS and Siemens Calibre DRC/LVS), with strong proficiency interpreting and correcting ERC, DRC and LVS error reports
Strong communication skills to effectively collaborate with cross-functional teams and external partners
Demonstrated strong technical project management skills with the ability to prioritize tasks, anticipate roadblocks, manage schedules, and deliver results in a fast-paced environment

Responsibilities

Leverage Top-Down Bottom-Up (TDBU) floorplan methodology to create and refine the RFID or Reader IC floorplan — collaborating with circuit and block-level layout designers on sizing, pin rings, inter-block routing, and full-chip channels — while maintaining order in layout hierarchy for streamlined development and tape-in
Work closely with the analog and digital design teams on floor planning, pin placement, power supply strategy and signal distribution between blocks
Coordinate with program managers and cross-functional teams — design, verification, packaging, manufacturing, and foundry — to track layout and floorplan activities to a predictable schedule and lead a successful, timely and quality tape-out
Conduct layout reviews for power/ground routing, electromigration, matching, and signal coupling/integrity, and complete full-chip closure activities, including seal-ring and bump integration, dummy fill, DRC, LVS, density, and DFM checks
Perform detailed transistor-level layout of RF, mixed-signal, and analog circuit blocks for both high-performance RF as well as ultra-low power and compact RFID
Participate in the IC layout methodology roadmap, collaborating with technology, CAD, and design teams to ensure successful deployment while balancing short-term execution with long-term strategic goals