Senior Staff Design Architecture Engineer

Renesas Electronics•Austin, TX

3d•Hybrid

About The Position

This role involves architecting and optimizing digital multiphase voltage regulators. The engineer will perform gain/phase margin and stability analysis, architect and design robust loop compensation, and model/simulate regulator behavior (steady-state & transients) using tools like Simplis, MATLAB, Simulink, and SystemVerilog. Key responsibilities include defining PWM modulation, phase-management, current sensing, and ripple minimization strategies. The role also requires modeling, implementing, and verifying control logic with SystemVerilog/Verilog, collaborating with analog, digital, and mixed-signal teams, and validating designs through small-signal and time-domain analysis to drive improvements in feedback systems.

Requirements

Deep understanding of feedback control, Bode/Nyquist, and stability criteria.
Strong DSP fundamentals applied to digital power control.
Proven modeling skills: behavioral, small‑signal, and system‑level.
Hands‑on with multiphase converters, PWM schemes, current‑balance, and transient optimization.
SystemVerilog/Verilog proficiency for RTL design and verification (UVM a plus).
B.S./M.S. in Electrical Engineering (Ph.D. a plus).
5–10+ years in power electronics, control systems, or digital multiphase regulation.

Nice To Haves

UVM a plus
Scripting in MATLAB/Python preferred.

Responsibilities

Architect and optimize digital multiphase voltage regulators.
Perform gain/phase margin and stability analysis; architect and design robust loop compensation.
Model and simulate regulator behavior (steady‑state & transients) in Simplis/MATLAB/Simulink/SystemVerilog.
Define PWM modulation, phase‑management, current sensing, and ripple minimization strategies.
Model/Implement/verify control logic with SystemVerilog/Verilog; collaborate across analog, digital, and mixed‑signal teams.
Validate designs via small‑signal and time‑domain analysis; drive improvements to feedback systems.