Senior Staff Collateral Design and DFM Engineer

Intel•Phoenix, CA

1d•$161,550 - $317,600•Hybrid

About The Position

Manufacturing Development Customer Engineering (MDCE) is Intel's newest organization within Intel Foundry Technology Manufacturing (FTM). We bridge the critical gap between Technology Development (TD) and High-Volume Manufacturing (HVM), advancing technology nodes from initial product qualification to high-yield production across multiple products while enhancing technologies for our foundry customers. Intel's Chandler, Arizona facility is constructing state-of-the-art fabrication facilities for cutting-edge technology nodes, including Intel 18A and beyond. Additionally, we're developing legacy technologies with foundry partners to launch HVM operations serving global foundry customers. We seek an experienced Senior Staff Collateral Design and DFM Engineer to join our MDCE team and help build a world-class Foundry Customer Engineering organization. In this role, you will be at the forefront of high-volume manufacturing (HVM) and ramp leading-edge advanced logic technologies. You will play a pivotal role in inventing and enhancing Design for Manufacturability (DFM) methodologies that drive measurable improvements in performance, yield, and ramp speed across a broad and dynamic product portfolio.

Requirements

Master’s in Electrical Engineering, Physics, or a closely related field
6+ years of experience in DTCO and/or DFM within a semiconductor foundry or advanced technology development environment
Experience in DTCO methodologies, including SRAM and Standard Cell design
Experience leading cross-functional teams in defining derivative architectures encompassing design rules, transistors, and interconnects
Hands-on experience in advanced node test chip design and scribe line optimization across 3nm–16nm FinFET or sub-3nm GAA FET technologies, including Backside Power Delivery (BSPD)

Nice To Haves

Ph.D. in Electrical Engineering, Physics, or a closely related field
Experience in scripting and coding for design automation and flow development
Experience with physical design flows for yield analysis, DRC, and verification
Experience in a foundry environment delivering DFM solutions for varied customer requirements across multiple market segments
Experience with the foundry ecosystem, including customer design flows and manufacturing constraints across diverse application domains

Responsibilities

Lead cross-functional teams spanning Process Integration, Device, Yield, Design, OPC/RET, Design Rules, DTP, and CAD to define and continuously enhance DFM rules that accelerate yield improvement and technology ramp on advanced logic nodes
Translate silicon learning and yield insights into actionable feedback for design teams, enabling timely updates to layout and DTCO methodologies and flows that catch yield issues earlier in the design cycle
Develop, refine, and optimize yield tools and flows within the foundry environment, supporting inline yield detection and continuous process optimization
Define and evolve DFM methodologies by deeply understanding silicon process flows, predicting layout and design marginalities, and collaborating with cross-functional partners to develop robust mitigation rules
Drive scribe line layout design and process monitoring structure development to support advanced node characterization and manufacturing readiness
Manage design rule development, validation, and waiver processes, ensuring alignment between manufacturing constraints and customer design requirements
Serve as the key interface between Process Integration, Yield, Device, and Design teams acting as a trusted technical bridge across all stakeholders
Support foundry customers across multiple market segments by developing and implementing tailored DFM solutions that meet diverse application requirements