Senior Speed and Reliability Codesign Engineer

NVIDIA•Austin, CA

9d•Hybrid

About The Position

NVIDIA builds the accelerated computing platforms that train and run the world's largest AI models. Whether a chip sustains its target frequency and lifetime — after every power, thermal, and reliability margin is paid — decides how much real performance reaches the datacenter! We are the Silicon Co-Design Group. We are hiring a Senior Speed and Reliability Codesign Engineer to build speed and reliability features into the silicon and to prove, against real silicon, that they deliver. We own the codesign space where architecture, design, and manufacturing meet, and we make the whole system perform. If this sounds like something you want to do, read on!

Requirements

BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or equivalent experience.
10+ years in silicon design, performance, timing, or post-silicon speed validation, with hands-on depth in both timing and real silicon.
A track record of taking features from concept through silicon validation, with measured results.
Comfortable working both sides of the boundary — enough design depth to build, and enough data fluency to correlate against silicon.
Familiarity with silicon margining and guard-banding is essential.
Cross-functional influence, with a demonstrated ability to align architecture, design, and manufacturing without direct reporting authority.
Excellent problem solving, partnership, and interpersonal skills.

Nice To Haves

Closed the loop between predictions and silicon results, with a correlation methodology other teams adopted
Designed or integrated on-die sensors/actuators (droop detectors, aging monitors, adaptive clocking, telemetry)
Datacenter-scale or high-performance silicon experience
Applied ML or data-driven techniques to silicon performance, reliability modeling, or design-space exploration
Patents, publications, or standards contributions in silicon performance or reliability

Responsibilities

Build out speed and reliability features from on-chip building blocks — on-die clocking, droop detection, and aging monitors — that protect frequency and lifetime without spending extra power or margin.
Own design-to-silicon correlation. Tie pre-silicon predictions — VF curve, Vmin and Vmax, timing and aging margins — to measured silicon, and feed the gaps back to design.
Verify the codesign. Prove each feature holds across voltage, temperature, process, and aging corners before tapeout — verification is part of how we design, not a later step.
Use AI as a force multiplier. Build AI-driven flows for correlation, data analysis, and verification that compress cycle time and catch issues earlier.
Drive decisions across the silicon-to-system boundary. Surface where a feature trades frequency or lifetime against power, yield, or area, and bring the data that settles the call.
Collaborate with architecture, VLSI, ASIC, firmware, and product teams to bring next-generation products to market.