Senior Software Architect, Physical AI

Altera Semiconductor•San Jose, CA

2d•Onsite

About The Position

Altera is seeking a Senior Software Architect to help build our Physical AI SDK—a developer-facing platform that enables robotics and drones applications to use FPGA acceleration through portable, composable, high-performance APIs. You will connect frameworks such as NVIDIA Holoscan, ROS 2, Linux, and ONNX Runtime to Altera FPGA platforms. This hands-on role combines software architecture, production development, hardware/software integration, and customer-focused solution delivery.

Requirements

Bachelor's Degree in Computer Science, Computer Engineering, Electrical Engineering, or a related field, plus 15+ years of relevant experience.
Strong C++ and Linux systems-development skills, including concurrency, performance optimization, and debugging.
Experience designing and shipping SDKs, middleware, runtimes, device frameworks, or developer-facing platform software.
Understanding of heterogeneous data movement across CPU, GPU, FPGA, DMA, shared memory, and high-speed I/O.
Experience with Holoscan, ROS 2, GStreamer, ffmpeg, OpenCV, or a comparable robotics or real-time framework.
Experience with hardware-accelerated video, vision, sensor, networking, or signal-processing pipelines.
Strong communication skills and demonstrated ownership of complex, cross-functional projects.
Applicants must be eligible for any required U.S. export authorizations.

Nice To Haves

Experience with Altera FPGAs, PCIe, Ethernet, MIPI CSI-2/D-PHY, GMSL, FPGA acceleration, or HLS/RTL integration.
Experience with robotics end-to-end pipeline.
Familiarity with zero-copy, RDMA, GPUDirect, high-speed Ethernet, embedded Linux, Yocto, containers, and cross-compilation.
Experience with camera systems, ISP pipelines, video compression, sensor fusion, SLAM, or robotics perception.
Experience defining SDK roadmaps, compatibility policies, release criteria, and developer documentation.

Responsibilities

Define and guide SDK architecture, APIs, hardware abstraction, device discovery, lifecycle management, diagnostics, and plugin interfaces.
Architect high-performance modules for sensor ingestion, camera and video pipelines, ISP, compression, memory and buffer management, synchronization, networking, localization, and AI pre-processing.
Work with the engineering to integrate FPGA acceleration into Holoscan and ROS 2 workflows, including minimum or zero-copy data paths, DMA, metadata, timestamping, QoS, and deterministic execution.
Help develop Linux-based C++ libraries, Python bindings, utilities, deployment tools, and take responsibility of documentation, and reference applications.
Collaborate with FPGA, hardware, AI, systems, and customer teams to validate latency, throughput, resource utilization, and reliability.
Mentor engineers and provide technical leadership from architecture through release.