Senior SOC Physical Design Engineer
About The Position
This individual independently plans, performs the moderately-defined responsibility for the Physical Design Flow of high-speed DDR, graphics, physical verification flows, microarchitecture, SOC algorithm design and modeling, and methodology, focusing on target power utilization and optimization for system-on-chip (SoC) products and how these features impact power and performance. Responsibilities include: Floor Planning, Clock Tree Synthesis, Place and Route, PDN, Timing analysis and closure. Performs various physical verification checks (such as LVS, DRC, design-for-manufacturing & design-for-yield) at the chip and block levels. Provides schedules and support cross-functional engineering effort to drive to signoff closure for tapeout. Acts as a strong contributor at design reviews and project meetings.
Requirements
- High-speed DDR
- graphics
- physical verification flows
- microarchitecture
- SOC algorithm design and modeling
- methodology
- target power utilization and optimization
- impact power and performance
- LVS
- DRC
- design-for-manufacturing
- design-for-yield
Responsibilities
- Floor Planning
- Clock Tree Synthesis
- Place and Route
- PDN
- Timing analysis and closure
- Performs various physical verification checks (such as LVS, DRC, design-for-manufacturing & design-for-yield) at the chip and block levels
- Provides schedules and support cross-functional engineering effort to drive to signoff closure for tapeout
- Acts as a strong contributor at design reviews and project meetings
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What This Job Offers
Job Type
Full-time
Career Level
Senior
