Senior Silicon Design Verification Engineer

Microsoft•Mountain View, CA

About The Position

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is responsible for Microsoft's expanding Cloud Infrastructure, powering services like Bing, Office 365, Xbox Live, Teams, OneDrive, and Microsoft Azure. The Compute Silicon & Manufacturing Engineering (CSME) organization within SCHIE designs, develops, manufactures, and packages Microsoft's advanced computer chips, including Azure Cobalt. The Shared and Custom IP & Silicon (SCIPS) team focuses on defining and delivering operational measures for hardware manufacturing, improving planning, quality, delivery, scale, and sustainability for Microsoft cloud hardware. This role is for a Senior Silicon Design Verification Engineer within the SCIPS team, contributing to customer-focused solutions and future technical implementations for cloud infrastructure management and optimization.

Requirements

Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR equivalent experience.
Screening Requirements: Ability to meet Microsoft, customer and/or government security screening requirements.
Microsoft Cloud Background Check: Required upon hire/transfer and every two years thereafter.
Export Control Regulations: Must provide proof of country of citizenship or US residency for eligibility to access export-controlled information. Citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents.

Nice To Haves

Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR equivalent experience.
Experience developing C and C++ test content for subsystem and SoC verification, including bare-metal and firmware-style tests, with working knowledge of SystemVerilog testbenches.
Experience bringing up and maintaining FPGA prototyping or emulation platforms (such as HAPS or Xilinx), including board images, platform tooling, and testbench changes that enable firmware and validation teams.
Hands-on hardware debug experience with tools such as JTAG debuggers, logic analyzers, oscilloscopes, and multimeters.
Experience owning pre-silicon verification of IP, subsystems, or SoCs through the full cycle, including test planning, test development, failure debug, and coverage signoff.
Experience with post-silicon bring-up and validation, including running test suites on silicon and debugging boot, platform, and connectivity issues in a lab environment.
Proficiency in Python, or a similar scripting language such as Perl or Ruby, for test automation, build flows, and log or data parsing.
In-depth knowledge of verification principles, testbench architecture, and stimulus generation, with a track record of debugging complex designs.
Experience with low-level and embedded software, including assembly, startup code, linker scripts, and Makefile-based build flows.
Familiarity with industry protocols such as AMBA (AXI/AHB/APB), JTAG, SPI, I2C/I3C, and USB.
Experience collaborating across architecture, design, firmware, and validation teams, with strong communication skills.
Understanding of silicon and/or computer architecture.

Responsibilities

Develop C and C++ based test content, low-level drivers, and custom firmware at the subsystem and SoC levels, including self-checking tests that run on embedded processors.
Extend the compile and build flow to support custom firmware-style tests.
Serve as a technical owner for the team's FPGA prototyping platforms (such as HAPS or Xilinx): create board images and bit files.
Design additional custom FPGA RTL for protocol interfaces and feature enablement.
Release stable platforms to the firmware team and keep them working as the design evolves.
Develop and extend custom python tooling to interface with the FPGA platform.
Debug FPGA and post-silicon issues using tools such as JTAG debuggers, logic analyzers, oscilloscopes, and multimeters.
Drive post-silicon bring-up and validation in the lab: run the validation suites on first silicon, meet bring-up exit criteria on schedule, and debug platform issues such as JTAG failures, UART connectivity, and boot failures alongside the design, firmware, hardware, and security teams.
Root-cause failing post-silicon tests to closure, collecting and analyzing scan dumps for low-level issues such as boot ROM and built-in self-test bugs, coordinating cross-team debug, and delivering fixes such as handling fatal errors, correcting driver access violations, and reconciling registers modified by boot firmware.