Senior Semiconductor Design Engineer

Micron • San Jose, CA

11h

About The Position

Design and develop non-volatile 3D-NAND memory array drivers and sensing circuits. Plan wordline and bitline path architecture according to area, performance, and power specifications. Generate X-path, Y-path, SRC-path and Array schematics and integrate into full-chip schematics. Generate simulation decks and run block-level, subsystem, and full-chip simulations to confirm functionality and validate performance targets using industry-standard tools (e.g., HSPICE, XA Fast Spice). Floorplan and oversee layout implementation and integration of circuit blocks into the chip plan. Develop array waveforms with detailed timing and biasing conditions for 3D-NAND memory read, program, and erase algorithms. Work closely with Firmware, Analog, Design Validation, Process Integration, and Product Engineering teams. Collaborate during silicon debug and diagnose circuit and array failures, determine root causes of silicon issues, and apply corrective actions. Develop and implement automation tools to improve work efficiency, accuracy, and reliability in memory circuit design. Prepare user documentation and specifications for new circuits. Participate in design reviews and technical presentations. Mentor and train junior engineers in simulation, modeling, and design methodologies.

Requirements

• Master’s degree in Electrical Engineering, Computer Engineering, Physics, or related field and 2 years of experience in the job offered or related occupation.
• Developing automation frameworks, simulation methodologies, and design tools for semiconductor applications
• Post-silicon debug and product validation
• Analog and digital circuit design, layout optimization, and device physics
• Semiconductor memory architecture, circuit modeling, and simulation
• Verilog, HSPICE, and XA Fast Spice simulation tools
• Lavis and ParagonX post-layout verification tools
• Unix and Windows scripting and developing tools for design automation and results analysis
• Python

Responsibilities

• Design and develop non-volatile 3D-NAND memory array drivers and sensing circuits.
• Plan wordline and bitline path architecture according to area, performance, and power specifications.
• Generate X-path, Y-path, SRC-path and Array schematics and integrate into full-chip schematics.
• Generate simulation decks and run block-level, subsystem, and full-chip simulations to confirm functionality and validate performance targets using industry-standard tools (e.g., HSPICE, XA Fast Spice).
• Floorplan and oversee layout implementation and integration of circuit blocks into the chip plan.
• Develop array waveforms with detailed timing and biasing conditions for 3D-NAND memory read, program, and erase algorithms.
• Work closely with Firmware, Analog, Design Validation, Process Integration, and Product Engineering teams.
• Collaborate during silicon debug and diagnose circuit and array failures, determine root causes of silicon issues, and apply corrective actions.
• Develop and implement automation tools to improve work efficiency, accuracy, and reliability in memory circuit design.
• Prepare user documentation and specifications for new circuits.
• Participate in design reviews and technical presentations.
• Mentor and train junior engineers in simulation, modeling, and design methodologies.

Benefits

• Choice of medical, dental and vision plans
• Benefit programs that help protect your income if you are unable to work due to illness or injury
• Paid family leave
• Robust paid time-off program
• Paid holidays

What This Job Offers

• Job Type: Full-time
• Career Level: Senior
• Number of Employees: 5,001-10,000 employees