Senior Principal Telemetry and Flight Terminations Engineer

RTX•Tucson, AZ

12d•Onsite

About The Position

At Raytheon, the foundation of everything we do is rooted in our values and a higher calling – to help our nation and allies defend freedoms and deter aggression. We bring the strength of more than 100 years of experience and renowned engineering expertise to meet the needs of today’s mission and stay ahead of tomorrow’s threat. Our team solves tough, meaningful problems that create a safer, more secure world. Raytheon’s Effector Analog & Power (EAP) Team is seeking a Senior Principal Telemetry & Flight Termination Systems (TM/FTS) Engineer to serve as a technical authority, drive strategic architecture decisions, and lead development of next‑generation Telemetry and Flight Termination Systems. The Effector Power Department is responsible for the development, from concept to integration, of Telemetry and Flight Termination products; power systems from all up round to the lowest level power regulation; servo electronics supporting all mechanical motion in our products and low noise mixed signal electronics that provides the analog to digital interface to our front-end sensors. Each of these products generally operate in lower power and voltage ranges less than 10kW and 1000V. The TM/FTS team develops system designs focused on supporting effector flight tests. We adhere to rigorous standards from the Range Commanders Council, Federal Communications Commission, and the National Security Agency in the design and utilization of our products.

Requirements

Bachelor’s degree in Science, Technology, Engineering, or Mathematics (STEM) and a minimum of 10 years of relevant experience; or Advanced degree in STEM and a minimum of 7 years of relevant experience.
Experience in system‑level and/or subsystem‑level electronics design.
Experience in generating, interpreting, and/or managing electrical design specifications.
Experience in analog and mixed‑signal electronic design (FET/BJT circuits, op‑amps, filters, terminations, comparators, A/D converters, level shifting, load switching, etc.).
Experience with engineering analysis tools such as MATLAB, MathCAD, Mathematica, or similar.
Active and transferable U.S. government issued security clearance is required prior to start date.
U.S. citizenship is required, as only U.S. citizens are eligible for a security clearance.
Ability to obtain INTERIM U.S. government issued security clearance is required prior to start date.

Nice To Haves

Advanced degree in Electrical Engineering
Extensive experience applying government regulations such as RCC standards, FCC requirements, NSA guidance, and DoD/Range safety criteria.
Experience with component‑level qualification, including environmental, EMI/EMC, radiation, and reliability-related testing.
Demonstrated experience leading cross‑functional engineering teams.
Deep technical expertise with: Mixed‑signal PCB design
RF/antenna interfaces
RF transmitters and receivers
ECAD workflows and layout/routing considerations for TM/FTS
Strong laboratory diagnostic and test experience.
Experience with: Microcontroller, FPGA, and digital interface design
System grounding schemes and resolving ground reference issues
Requirements development and test plan creation
Electrical interface control documents
Power supply design
Detailed printed circuit board layout

Responsibilities

Serve as the chief technical lead for TM and FTS architectures, guiding design direction across programs.
Act as the Responsible Engineering Authority (REA) for high‑criticality TM/FTS hardware.
Lead major design efforts from concept through integration, qualification, and mission support.
Define and champion technology roadmaps for TM, FTS, and mixed‑signal effector electronics.
Lead cross‑functional engineering teams to resolve complex design, integration, and field issues.
Direct supplier engagements, technical negotiations, and make/buy trade studies.
Oversee creation of requirements, architectures, analyses, and compliance documentation for internal and government reviews.
Mentor and develop junior, mid‑level, and principal engineers; guide engineering best practices across the department.