Senior Principal RFIC Design Engineer

Western Digital•San Jose, CA

1d•Onsite

About The Position

WD is building the infrastructure behind the AI-driven data economy. As AI scales, so does data. Every interaction, every model, every system generates data that must be stored, managed, and made accessible over time. That’s where we come in. We combine deep engineering expertise with global-scale manufacturing to deliver the storage systems that make AI possible, powering hyperscale data centers, cloud platforms, and enterprise infrastructure worldwide. This isn’t theoretical work. It’s real systems, at real scale, people solving some of the hardest challenges in technology today. We’re looking for people who want to build, solve, and operate at that level. Join us and let’s shape the future of data. ESSENTIAL DUTIES AND RESPONSIBILITIES: Designer will be responsible for the design of high performance RF and analog circuit blocks. Responsibilities include transistor level, block level and module level circuit architecture, design, simulation, optimization, layout supervision, layout verification, preparation of test plan for the testing team, reliability and yield assessment and modeling, simulation to bench and bench to test correlation, bench evaluation both at silicon level and at applications level, and documentation. Job responsibilities require ability to communicate at all levels and with cross functional groups. Candidate must have good verbal and written communications skills and demonstrated track record of circuit innovation, must be a team player, be adaptable, and accept constructive feedback.

Requirements

Must have hands-on design and development experience in RF and analog integrated circuit.
Must have experience in at least one preferably multiple area of full CMOS circuit design and development in: Baseband amplifiers, low noise RF amplifiers, wide bandwidth amplifiers, Mixers, up-converters, down-converters, High speed drivers and receivers, CDR circuits, equalizers, Power amplifiers.
Must have experience in 40nm and below CMOS technology.
Must have a demonstrable track record of successful design releases and mass production.
Must have thorough knowledge of industry standard EDA tools (Cadence, Mentor, Siemens, Ansys etc.).
Experience with RF and high performance analog block layout such as LNA, mixer, analog to digital converters, references, digital to analog converters etc.
Experience with floor planning, block level routing and top level chip routing.
Knowledge of high performance analog layout considerations such as matching, EM-IR and SOA and mitigation techniques.
BS, MS or PhD with relevant experience.
Strong written and verbal communication skills.

Nice To Haves

Experience working with distributed design teams a plus.

Responsibilities

Design of high performance RF and analog circuit blocks.
Transistor level, block level and module level circuit architecture, design, simulation, optimization, layout supervision, layout verification.
Preparation of test plan for the testing team.
Reliability and yield assessment and modeling.
Simulation to bench and bench to test correlation.
Bench evaluation both at silicon level and at applications level.
Documentation.
Communicate at all levels and with cross functional groups.

Benefits

Paid vacation time
Paid sick leave
Medical/dental/vision insurance
Life, accident and disability insurance
Tax-advantaged flexible spending and health savings accounts
Employee assistance program
Other voluntary benefit programs such as supplemental life and AD&D, legal plan, pet insurance, critical illness, accident and hospital indemnity
Tuition reimbursement
Transit
The Applause Program
Employee stock purchase plan
The WD Savings 401(k) Plan