Senior Principal Platform Architect

Renesas Electronics•San Jose, CA

12h•$253,000 - $315,000•Onsite

About The Position

As the Senior Principal Platform Architect for UALink Switch Products, you will be the ultimate system-level authority responsible for defining the end-to-end hardware, software, and management architecture of our next-generation AI scale-up network chassis. In this role, you will look beyond the individual switch silicon to architect the entire platform ecosystem. You will define how multiple UALink switch ASICs interact across backplanes, determine how the system handles multi-kilowatt power delivery and liquid/air cooling orchestration, and architect the platform management stack (BMC/OpenBMC) that allows the switch to seamlessly integrate into massive hyper-scale data centers. You will bridge the gap between silicon engineering, system hardware design, and cloud software orchestration.

Requirements

Master’s or Ph.D. in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
20+ years of architectural experience in high-performance server platforms, hyper-scale network switches, or data center infrastructure.
Expert knowledge of high-speed platform fabrics and standards (UALink, NVLink, OAM/UBB, PCIe Gen6/Gen7, CXL, or Ultra Ethernet).
Deep expertise in industry-standard management architectures, including Redfish, IPMI, MCTP, SPDM, and OpenBMC.
Thorough understanding of OS/VMM kernels, device drivers, and platform initialization frameworks (UEFI, ACPI).
Comprehensive grasp of modern rack architectures (e.g., OCP ORv3), liquid cooling management, and high-density 48V/54V power delivery.

Nice To Haves

Proven track record of delivering a high-volume, multi-million-gate switching or compute platform successfully into top-tier hyper-scale cloud providers (AWS, Azure, GCP, Meta).
Active committee leadership or direct specification contributions within the UALink Consortium, Ultra Ethernet Consortium (UEC), or Open Compute Project (OCP).
Experience architecting systems designed for ultra-high-density accelerator form factors (such as Nvidia Blackwell/Vera Rubin grids or AMD Instinct platforms).

Responsibilities

Lead the structural, electrical, and logical design of the UALink switch chassis, defining high-speed backplane topologies, cabled scale-up fabrics, and multi-tier switch hierarchies.
Partner with electrical and SI/PI engineering teams to define parameters for ultra-high-speed SerDes routing across PCBs, flyover cables, and optical components, minimizing bit error rates (BER).
Architect rack-level and row-level topologies that optimize collective communication paths (e.g., All-Reduce, All-to-All) for tens of thousands of interconnected GPUs.
Architect the end-to-end system management plane. Define how Baseboard Management Controllers (BMCs) monitor, configure, and provision the switch using OpenBMC, Redfish, and PLDM over MCTP.
Establish platform-level boot sequencing, multi-rail power sequencing, and secure multi-node firmware update orchestration.
Define the hardware security lifecycle, including Platform Firmware Resiliency (NIST SP 800-193), secure enclave integration, and Component Attestation (SPDM).
Architect system-level Reliability, Availability, and Serviceability (RAS) strategies. Define how the platform isolates hardware faults, routes around failed links, handles hot-swapping of fans, power supplies, and switch blades without dropping the AI training cluster.
Establish dynamic power management and telemetry frameworks to balance the massive transient power draws of next-generation AI workloads against rack-level cooling limits.