Senior Principal Engineer

Altera • San Jose, CA

23h • $231,500 - $304,500 • Hybrid

About The Position

Altera is looking for a Senior Principal Engineer to serve as a key technical leader responsible for defining and advancing FPGA physical synthesis, timing optimization, and implementation methodologies. This individual will bring deep expertise in EDA algorithms, optimization engines, design compilation, and performance-driven implementation technologies. The ideal candidate will have a proven track record of architecting and delivering breakthrough technologies that significantly improve quality of results (QoR), runtime, scalability, and customer productivity for large-scale FPGA or ASIC designs. This role offers the opportunity to influence the long-term technical direction of Altera's FPGA software platform and collaborate with world-class engineers solving some of the industry's most complex optimization challenges.

Requirements

• BS, MS, or PhD in Electrical Engineering, Computer Science, Computer Engineering, or a related technical field.
• 15+ years of experience developing EDA software, FPGA tools, ASIC implementation tools, or related optimization technologies.
• Deep expertise in one or more of the following domains: Physical Synthesis Timing Analysis Logic Synthesis Placement and Routing Design Optimization Algorithms FPGA Architecture and CAD Flows Static Timing Analysis Physical Design Implementation
• Demonstrated experience architecting large-scale software systems and optimization engines.
• Strong software development skills in C++, data structures, algorithms, and performance optimization.
• Proven ability to solve highly complex technical problems and deliver innovative solutions to production software environments.
• Experience influencing technical direction across multiple engineering teams.

Nice To Haves

• Experience developing commercial FPGA or ASIC implementation tools.
• Expertise in path-based optimization, timing-driven synthesis, or physical design methodologies.
• Experience improving tool QoR, runtime performance, or scalability for large customer designs.
• Background creating novel optimization algorithms that became widely adopted production technologies.
• Experience with machine learning applications for EDA optimization and implementation flows.
• Patent portfolio or significant technical publications in EDA, FPGA, or semiconductor design.
• Experience serving as a Distinguished Engineer, Architect, Fellow, or equivalent technical leadership role.

Responsibilities

• Define and drive the architectural roadmap for FPGA compiler technologies.
• Design and develop advanced optimization algorithms focused on timing closure, area reduction, power optimization, routability, and runtime improvement.
• Lead development of next-generation timing driven optimization methodologies.
• Architect scalable solutions for large hierarchical designs and complex FPGA implementation flows.
• Drive innovation across synthesis, placement, routing, timing analysis, and physical optimization domains.
• Partner with cross-functional engineering teams to integrate new technologies into production tool flows.
• Analyze customer workloads, benchmark results, and field feedback to identify high-impact improvement opportunities.
• Lead technical investigations of challenging timing and implementation problems across customer designs.
• Mentor engineers and provide technical leadership across architectural and algorithmic initiatives.
• Collaborate with product management and strategic customers to translate market needs into differentiated technology solutions.
• Contribute to patents, publications, and industry-leading innovations that strengthen Altera's competitive position.

Benefits

• The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc.
• We also offer incentive opportunities that reward employees based on individual and company performance.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior
• Education Level: No Education Listed