Senior Principal Engineer, Hardware Application Engineering — Board & System Design

Marvell Technology • Santa Clara, CA

2d • $177,820 - $266,400

About The Position

Marvell is hiring a senior technical leader in its U.S. Customer Solutions Group to guide customer hardware design-in for Marvell Ethernet Switch and UALink platforms. The role connects customer engineering teams with Marvell’s silicon and internal hardware engineering teams, helping turn silicon into deployable systems from early architecture through production ramp. Its focus is ensuring customer switches, AI fabric platforms, and networking systems are performant, manufacturable, reliable, and ready for high-volume production.

This is a deep individual-contributor role centered on system design and productization. The engineer will review and shape customer designs across board architecture, PCB stack-up and materials, power, thermal design, mechanical integration, reliability, and manufacturability, while retaining hands-on capability across architecture, schematic, layout guidance, and bring-up. The role also defines and supports reference designs for new silicon, provides technical education to customers and internal teams, and contributes to Marvell’s work on 224G and 448G SerDes-class systems and emerging open AI fabric standards.

The position includes technical leadership in strategic customer engagements, mentoring and training, roadmap input based on field experience, and representation of Marvell’s hardware capabilities to customers and partners. Travel to customer sites, ODMs, and labs may be required as projects demand; it is typically project-driven rather than continuous.

Requirements

• PhD, Master’s, or Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field.
• 15+ years of experience in hardware design, development, and validation of high-speed networking or compute systems.
• 7+ years of dedicated board and system design experience for high-speed platforms using modern SerDes, from 25G NRZ through 112G/224G PAM4.
• Proven full-lifecycle ownership of complex high-speed boards, including architecture, schematic, layout guidance, and bring-up.
• Demonstrated experience defining and delivering reference designs that enabled customer or internal platform adoption.
• Strong expertise in PCB stack-up design and material selection for high-speed, high-layer-count boards.
• Deep experience with power architecture for high-current ASICs, including PDN design, sequencing, decoupling, and tolerance analysis.
• Solid background in thermal design and mechanical integration for high-power network and AI systems.
• Working knowledge of SI/PI principles, including reviewing customer simulations and independently running targeted simulations when needed.
• Hands-on hardware bring-up, lab debugging, and root-cause analysis experience using industry-standard lab equipment.
• Deep understanding of high-speed interfaces, including Ethernet, PCIe, DDR, advanced SerDes, and modern power delivery architectures.
• Strong grasp of design for reliability, manufacturability, and testability across the product lifecycle.
• Customer-facing experience supporting complex technical engagements and resolving deployment issues.
• Proven ability to develop and deliver technical training content to engineering audiences.
• Excellent communication skills and ability to influence senior customer engineering teams and collaborate across disciplines and geographies.
• Ability to travel as needed to customer sites, ODMs, and labs.
• Eligibility to access export-controlled information under applicable U.S. law; some applicants may be subject to an export license review process.

Nice To Haves

• Direct experience with Ethernet switch platforms and/or emerging open AI fabric standards and architectures.
• Experience designing or reviewing platforms targeting megascale data center deployments.
• Background in reference platform design and customer enablement for silicon-based solutions.
• Familiarity with ODM/CM manufacturing flows, including DFM/DFT, qualification, and reliability testing.
• Experience with advanced cooling approaches, including liquid and immersion cooling, for high-power AI/networking platforms.
• EDA tool fluency in Cadence (Allegro/Sigrity) or Mentor/Siemens (Xpedition/HyperLynx) ecosystems; tool-agnostic candidates with deep expertise are welcome.
• Track record of influencing silicon and platform roadmaps based on customer and field insights.

Responsibilities

• Serve as senior technical advisor to customer hardware teams designing platforms around Marvell Ethernet switches and UALink silicon, from early architecture through production ramp.
• Lead reviews of customer schematics, PCB stack-ups, and system architectures; identify risks and guide customers toward strong implementations.
• Define, develop, and support reference designs for new Marvell silicon, collaborating with silicon, packaging, and internal hardware engineering teams from product definition through customer release.
• Relay field feedback to internal hardware and silicon teams and influence silicon I/O, package, power, and reference design choices based on customer deployment experience.
• Drive PCB stack-up strategy and material selection, including low-loss laminates, copper roughness, glass weave, and via construction, to meet high-speed performance and cost targets.
• Own architecture, schematic, layout guidance, and bring-up of Marvell reference and evaluation platforms, applying hands-on expertise across the design lifecycle as needed.
• Guide customers on power delivery architecture, including PDN design, multi-rail sequencing, decoupling strategy, and tolerance analysis for high-current ASICs.
• Advise on thermal design, mechanical integration, and air, liquid, and immersion cooling strategies to meet deployment performance and reliability targets.
• Provide signal and power integrity guidance, review customer simulations, and contribute simulations when required.
• Drive design for reliability, manufacturability, and testability, supporting smooth production transitions at ODM/CM partners.
• Develop and deliver technical training for customers and internal teams on Marvell silicon, reference designs, high-speed design practices, and productization methodologies.
• Provide technical leadership on 112G and 224G PAM4 SerDes designs and help shape Marvell’s hardware approach for next-generation 448G systems.
• Lead hardware bring-up support, root-cause debugging, and issue resolution during customer lab phases and early production.
• Partner with Silicon Design, Packaging, SI/PI, Software, and Operations teams to deliver integrated solutions.
• Contribute customer feedback to product definition and roadmap planning, including architecture and marketing discussions.
• Represent Marvell hardware expertise in customer briefings, executive reviews, and industry technical forums.
• Set the technical bar for board and system hardware design quality across strategic customer engagements.
• Mentor engineers and lead training for customers and internal stakeholders.
• Shape customer-facing hardware solutions and influence next-generation product evolution.
• Travel as needed to customer sites, ODMs, and labs; travel is typically project-driven rather than continuous.

Benefits

• Eligible to participate in Marvell’s bonus and equity plans, including a new-hire equity grant and annual equity refreshers.
• Employee stock purchase plan with a 2-year look back.
• Family support programs.
• Mental health resources.
• Recognition and service awards.

What This Job Offers

• Job Type: Full-time
• Career Level: Senior