Senior Principal Engineer, Hardware Application Engineering — Signal Integrity & Power Integrity

YK Solutions•Santa Clara, CA

4d•Onsite

About The Position

Our Client's U.S. Customer Solutions Group is the frontline technical partner to the world's most demanding infrastructure customers — megascale data centers, cloud providers, and AI system builders. We turn silicon into deployable platforms by working shoulder-to-shoulder with customer engineering teams from early architecture through production ramp. Our engineers bring deep, hands-on expertise across hardware, software, and system integration. The close, trust-based collaboration we build with our customers — and with our Client's silicon and engineering hardware teams — is foundational to our Client's growth in networking, connectivity, and AI infrastructure. As Senior Principal Engineer for Signal Integrity and Power Integrity, you will be the senior technical authority responsible for ensuring that customer platforms built on our Client's Ethernet Switch and UALink silicon meet the highest performance and quality threshold — from first prototype through mass-production deployment. This is a deep individual contributor role with high customer and ODM visibility. Your mission is to implement best-in-class SI and PI practices across every Client-based platform you touch, so that performance is guaranteed across hundreds of thousands of units in real-world deployments. You will own layout guideline definition, post-silicon channel extraction and simulation, compliance testing, and SerDes tuning guidance, while also reviewing customer PDN designs and feeding learnings back to our Client's silicon and hardware engineering teams as part of a continuous improvement loop. You will be a key technical voice in our Client's evolution toward 224G and 448G SerDes-class systems and the emerging open AI fabric standards.

Requirements

PhD, Master's, or Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field.
15+ years of experience in hardware design, development, and validation of high-speed networking or compute systems.
10+ years of focused experience in signal integrity and power integrity work on high-speed SerDes platforms (25G NRZ through 112G/224G PAM4).
Demonstrated expertise across the full SI lifecycle: channel modeling and budgeting, layout and stack-up guideline definition, post-layout extraction and simulation, design-fix recommendations, and compliance/tuning guidance.
Strong PI capability — able to independently run and review PDN simulations covering impedance, IR drop, decoupling, transient response, and droop, and translate results into customer guidance.
Fluency across the leading SI/PI EDA toolchains (Ansys HFSS/SIwave, Cadence Sigrity/Clarity/PowerSI, or equivalent) — comfortable picking up and using whichever tools the project demands.
Strong hands-on lab expertise: VNAs, BERTs, real-time and sampling oscilloscopes, TDR, jitter analyzers, and high-speed compliance test kits — with proven debug capability in customer and internal lab environments.
Customer-facing experience supporting complex technical engagements and resolving real-world deployment issues.
Proven ability to develop and deliver technical training content to engineering audiences.
Excellent communication skills, with the ability to influence senior customer engineering teams, ODM engineers, and internal stakeholders across disciplines and geographies.

Nice To Haves

Direct experience with Ethernet switch platforms (any tier) and/or emerging open AI fabric standards and architectures.
Experience supporting SI/PI for platforms targeting megascale data center deployments at production volume.
Background in reference platform SI/PI definition and customer enablement for silicon-based solutions.
Familiarity with ODM/CM design and qualification flows, including DFM/DFT, reliability testing, and high-volume manufacturing variability.
Experience defining SerDes tuning methodologies and correlating simulation, lab, and field-telemetry data.
Familiarity with chip-to-module, copper cable, and connector ecosystems relevant to high-speed Ethernet and AI fabric channels.
Track record of influencing silicon and platform roadmaps based on SI/PI insights from customer and field deployments.

Responsibilities

Serve as the senior SI/PI technical authority for customer platforms built on our Client's Ethernet switches and UALink silicon, from early channel definition through mass-production qualification.
Define and maintain layout and routing guidelines for high-speed SerDes channels, power delivery networks, and sensitive analog interfaces — and drive their adoption with customers, ODMs, and internal teams.
Perform post-silicon channel extraction, full-channel simulation, and what-if analysis on customer board designs, and recommend targeted layout and stack-up fixes that move designs from "passing" to "best-in-class margins."
Lead compliance testing and lab characterization — BER/SER, eye-opening margins, jitter, return loss, crosstalk — and translate measurement data into actionable design and SerDes-tuning guidance.
Provide SerDes tuning guidance to customers based on simulation results, lab measurements, and field telemetry; partner with our Client's silicon teams to refine tuning methodologies.
Run and review power integrity simulations covering PDN impedance, IR drop, decoupling effectiveness, transient response, and droop, and guide customers on robust PDN architectures for high-current ASICs.
Translate customer power needs and constraints into structured feedback for our Client's silicon, packaging, and platform engineering teams — closing the loop for continuous product improvement.
Engage directly with ODMs on SI/PI guidance, design reviews, and qualification activities, partnering with the global Customer Solutions Group and internal engineering teams.
Support definition and validation of reference designs for new our Client's silicon — owning the SI/PI side of the design from early channel budgeting through customer release.
Provide hands-on lab debug expertise during customer bring-up and production ramp, using VNAs, BERTs, real-time scopes, TDR equipment, jitter analyzers, and compliance test kits.
Develop and deliver SI/PI training to customers, ODMs, and internal our Client's teams — covering high-speed design best practices, simulation methodology, and lab debug techniques.
Provide technical leadership on 112G and 224G PAM4 SerDes designs today, and help shape our Client's SI/PI approach for next-generation 448G systems.
Partner closely with our Client's Silicon Design, Packaging, Board/System HW, Software, and Operations teams to deliver fully integrated solutions.
Contribute to product definition and roadmap planning by bringing real-world SI/PI insights into architecture and marketing discussions.
Represent our Client's SI/PI expertise in customer briefings, executive reviews, and industry technical forums.
Set the SI/PI technical bar across our Client's most strategic customer engagements, ensuring designs are not just compliant but production-robust.
Serve as a key technical interface between customers, ODMs, our Client's silicon teams, and internal hardware engineering — accelerating learning in all directions.
Mentor engineers across the team and lead SI/PI training for customers, ODMs, and internal stakeholders, raising collective expertise in high-speed design and validation.
Shape the direction of our Client's customer-facing hardware solutions and influence next-generation product evolution.
Act as a technical ambassador, representing our Client's hardware expertise to top-tier customers, ODM partners, and industry forums.
Travel as needed to customer sites, ODMs, and labs — typically project-driven rather than continuous.