Senior Principal Engineer Digital ASIC Design/Manager

KYOCERA External•San Diego, CA

5d•Onsite

About The Position

Kyocera International, Inc. is seeking a Senior Principal Engineer Digital ASIC Design to join our team in San Diego, CA. This role is responsible for the architecture of digital design, planning and implementing digital infrastructure, and overseeing the implementation, verification, emulation, and validation of designs. The engineer will identify high-risk areas, propose resolutions, drive methodology processes, and create requirement specification documents. Collaboration with external vendors and internal teams is crucial for developing plans for micro-architecture, verification, and emulation of digital modules. This position leads digital design projects from inception to production for mixed-signal ICs, including hiring and managing employees or contractors. The role involves architecting and designing digital control functionality that interfaces with I/O and analog functions, performing RTL design, synthesis, LINT, RDC/CDC, LEC, timing constraint development, static timing analysis, and PNR oversight. Additionally, the engineer will perform or oversee test plan development, digital verification, coverage analysis, post-silicon lab testing, mixed-signal verification, scan insertion, MBIST, and LBIST.

Requirements

BS or MS degree in Electrical Engineering with 15 years of industry experience in Digital ASIC design in complex multi-million gate architectures and deep submicron technologies, with majority of products with 1st silicon success
Proven technical leadership experience
Ability to work with cross-functional teams and contractors across geographical boundaries
Strong verbal, communication and organizational skills
Ability to improve digital design methodology to deliver high quality ICs on schedule
Experience with requirements development, design reviews and documentation
Experience with mixed-signal design methodology
System level experience with architectural tradeoffs for partitioning functions across software, embedded firmware, and custom RTL based hardware accelerators.
Experience with architectural tradeoffs for selecting/defining high-speed communication interfaces
Experience with the selection and integration of embedded processor cores (RISC-V or similar), memory systems, priority interrupt controller, etc.
Ability to perform area and power estimation
Experience with test plan development for pre-silicon verification/emulation and post silicon validation
Solid understanding of DFT architecture and familiarity with production test methods
In depth knowledge and extensive hands-on experience in digital RTL design (Verilog/System Verilog) and micro-architecture, linting, LEC, RDC/CDC, SDF gate simulation, revision control and tagged releases, scripting, bug tracking, synthesis, scan insertion, timing constraint development, floor planning, clock tree synthesis, timing closure, netlist ECOs, and digital verification.
Experience with foundry provided CMOS process and design kits, standard cell libraries and memory compilers
Experience setting up toolchains (compiler, debugger, etc.) for embedded processor cores
Experience developing embedded firmware (C and assembly language) for embedded processor cores for digital verification
Experience with co-simulation to verify debug interface operability with the tool chain
Experience with Synopsys and Cadence front-end and back-end tools, such as: Xcelium, Genus, Conformal, Innovus, Synopsys PrimeTime, Spyglass Lint, TetraMax
Ability to perform/oversee post silicon bench test of digital functions

Nice To Haves

Experience with UVM is a plus
Experience with digital design for PLL control/calibration is a plus
Experience with interfacing to ADC/DAC, trim/calibration algorithms and DSP is a plus

Responsibilities

Responsible for architecture of digital design.
Plan and implement digital infrastructure.
Plan, oversee, and execute implementation, verification, emulation, and validation of design.
Identify potential high-risk areas and present possible resolutions.
Drive methodology process and requirement specification documents.
Work with external vendors and internal teams in developing plans for micro-architecture, verification, and emulation of digital modules.
Lead digital design projects from inception to production for mixed signals ICs.
Hire and manage full-time employees or contractors to support projects.
Participate in RFIC design flow by architecting and designing digital control functionality which interfaces to I/O and analog functions.
Perform RTL design, synthesis, LINT, RDC/CDC, LEC, timing constraint development, static timing analysis for digital control logic, which includes off-chip and on-chip serial bus, interface to analog blocks, clock distribution, AMBA bus, state machine, memories, embedded processor cores (RISC-V), bus arbitration, DMA, registers, IO pads, synchronous, asynchronous access and control functions.
Perform project resource planning, detailed schedule development, milestone and task tracking.
Oversee PNR and ensure integrity of physical layer design.
Perform/oversee test plan development, digital verification, coverage analysis, and post silicon lab test.
Support mixed signal verification of design.
Perform/oversee scan insertion, MBIST and LBIST.
Perform any other related duties as required or assigned.