Senior/Principal ASIC Digital Design Engineer

Idaho Scientific•Boise, ID

About The Position

Life is Short. Solve Hard Problems with Cool People Idaho Scientific is the Goldilocks of technology firms, combining the spirit and growth of a startup, with a financial footing and safety of a stable corporation. The perks of working at Idaho Scientific include all the benefits you’d expect from an employer who prioritizes a balanced human experience: Competitive Pay Flexible Work Schedule Health Benefits and Insurance Retirement fund contributions Profit Sharing Generous Paid Time Off Policy Solve the Problem, Not the Symptom. Idaho Scientific designs and deploys secure system solutions through novel CPU design, crypto cores, purpose-built system-on-a-chip architectures and hardened operating systems. Our solutions are the foundation for how military systems and US critical infrastructure will remain safe and secure through unpredictable operating environments of the future. We need smart people like you to join us in solving hard problems that matter. What You'll Get To Do: Collaborate with team leaders to explore and clearly identify real problems and solutions. Develop and define the microarchitecture of new Idaho Scientific IP to optimize performance, I/O, power consumption, area utilization, recurring cost and security functions. Implement and simulate IP blocks in RTL using SystemVerilog, VHDL, and other languages. Integrate complex systems that instantiate both Idaho Scientific and third party IP. Contribute to all aspects of design success from specification to production. Apply our state-of-the-art IP to ASIC and FPGA products in the real world. Define and improve high-quality design methods and processes. Mentor and guide other ASIC design engineers.

Requirements

US Citizenship (no exceptions)
Proven work experience designing and fabricating an ASIC (no exceptions)
Ability to get a security clearance
Solid technical background with at least 5 years of experience in FPGA or ASIC product development
Ability to communicate clearly in person and in written documentation
Degree in Computer Engineering, Computer Science, Electrical Engineering or related field
In-depth knowledge and experience with digital architectures and design methods such as RTL coding, synthesis, place-and-route, timing closure, constrained-random and formal verification
Strong analytical and problem solving skills
Extreme attention to detail
A willingness to roll up one’s sleeves to get the job done
Skilled at working effectively with cross functional teams

Nice To Haves

US Security Clearance, Active or current within the last two years
In-depth understanding of microprocessor architectures
Working knowledge of applied cryptography and cyber security topics
Experience applying principles of cyber security to operational technology and embedded systems
Experience with SystemVerilog, VHDL, and Test-Driven Development principles

Responsibilities

Collaborate with team leaders to explore and clearly identify real problems and solutions.
Develop and define the microarchitecture of new Idaho Scientific IP to optimize performance, I/O, power consumption, area utilization, recurring cost and security functions.
Implement and simulate IP blocks in RTL using SystemVerilog, VHDL, and other languages.
Integrate complex systems that instantiate both Idaho Scientific and third party IP.
Contribute to all aspects of design success from specification to production.
Apply our state-of-the-art IP to ASIC and FPGA products in the real world.
Define and improve high-quality design methods and processes.
Mentor and guide other ASIC design engineers.