ASIC Digital Design Engineer

Teledyne Technologies-posted 10 days ago

Full-time • Mid Level

Goleta, CA

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Teledyne Technologies Incorporated provides enabling technologies for industrial growth markets that require advanced technology and high reliability. These markets include aerospace and defense, factory automation, air and water quality environmental monitoring, electronics design and development, oceanographic research, deepwater oil and gas exploration and production, medical imaging and pharmaceutical research. We are looking for individuals who thrive on making an impact and want the excitement of being on a team that wins. Job Summary: ASIC Digital Design Engineer: Oversees definition, design, verification, and documentation for ASIC development. Determines architecture design, logic design, and system simulation. Defines module interfaces/formats for simulation. Contributes to the development of multidimensional designs involving the layout of complex integrated circuits. Evaluates all aspects of the process flow from high-level design to synthesis, place and route, and timing and power use. Analyzes equipment to establish operation data, conducts experimental tests, and evaluates results. May also review vendor capability to support development.

Flow down and documentation of customer requirements
Perform digital design, timing design, and detailed digital simulations
Develop IC specifications & documentation
Requirements Capture & Documentation Translating system-level specs into digital requirements.
Creating detailed timing (setup/hold, pixel clocking) and block diagrams.
Creating risk assessments and traceability matrices.
RTL Front-End Design Behavioral modeling of digital controllers (e.g., pixel readout sequencing, windowing).
Finite State Machine and datapath design for ASIC modes.
Clock domain crossing and power-aware RTL coding (asynchronous resets, and multi-clock domains).
Modular and synthesizable SystemVerilog.
Synthesis & Optimization Logic synthesis with constraints (timing, area, power).
Multi-corner, multi-mode (MCMM) analysis.
DFT/ATPG insertion (scan chains, BIST for ASIC testability).
Clock/Power optimization for low-power ASICs.
Perform Back-End Physical Design as needed Floorplanning and power grid design.
Place and Route (APR) with congestion management.
Timing closure across PVT corners.
DRC, LVS, extraction and signoff.
Perform RTL Verification & Simulation as needed Functional verification with UVM testbenches, coverage driven verification(code/functional/toggle).
Assertion based checks for timing critical paths, and co-simulation with analog models (e.g., pixel array interfaces, Verilog-AMS).
Customer interface and design review presentations
Coordination with design team, analog design, and full custom IC cell layout
IC Device Test Support: Provide assistance (as required) to test engineering to perform test verification
Attention to Detail required while performing design, layout, verification and simulations
Collaboration and Teamwork required to coordinate with design team, analog design, and full custom IC cell layout team members
Knowledge of and Continuous Learning in the following Areas: Full Custom IC Layout Design and CAD tools Imaging Systems and Electro-Optical Components Digital design for CMOS technology Simulation tools such as SPICE Schematic Capture and simulation Digital Synthesis and RTL code development, implementation, and verification
Analytical Problem-Solving skills required in order to identify the root cause of difficult technical problems as well as analyzing alternate approaches and developing practical solutions to solve technical problems while performing complex IC designs.
Organization, Planning & Execution required to ensure adherence to detailed digital IC design process and documentation
Strong Communication Skills and Good Presentation required to support customer presentations. i.e. PDR, CDR
Innovation: must have the ability to develop new ideas and/or creative designs using innovative methodologies and/or concepts
Decision Making ; Must be self-directing and possess the ability to make decisions based on problem analysis and evaluation of alternatives, risks and consequences

B.S. in EE or Physics required
Minimum 5 years’ experience in IC design, circuit topology, digital schematic capture and simulation desired.
Strong Computer Skills: Word, Excel, Outlook and PowerPoint
Knowledgeable in ISO 9001 process and procedures
Advanced skills in IC Design CAD tools
Applicants must be either a U.S. citizen or PERMANENT Resident

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