Principal ASIC Design Engineer

Fortinet•Sunnyvale, CA

18h•$160,000 - $220,000

About The Position

Fortinet is looking for a passionate ASIC Designer to join our R&D team! This role involves working on cutting edge high performance ASIC design from specification to RTL implementation. The new member of our team will have direct involvement in designing complex and innovative technologies. This position offers a large scope of experience and direct involvement with the complex and innovative technology and in addition, there is the opportunity to work alongside a close-knit team of seasoned software, hardware and network processor developers.

Requirements

8 years or more networking or processor design experience
Strong track record of ASIC/FPGA design from concept to mass production
Hands on experience in Verilog HDL coding and verification
Experience of high performance ASIC/FPGA design from specification to system bring up
Experience with Altera/Xilinx FPGA architecture, tools and IP portfolio
Ethernet and TCP/IP networking concept and protocols knowledge
Knowledge of System Verilog and UVM verification methodology
Highly motivated, positive, detail oriented and responsible
Good team player and strong communication skills
MSEE/MSCS

Responsibilities

Develop network processing ASIC/FPGA architecture and micro architecture specification
Design high performance and high quality ASIC/FPGA design from specification to RTL implementation
Perform ASIC/FPGA verification, lint/cdc, synthesis, timing analysis and IP integration
Implement network packet processing system using Altera/Xilinx FPGA
Participate in system/board level bring up, debugging and support