Senior Power Systems Engineer

HP IQ•San Francisco, CA

4d•$170,000 - $240,000

About The Position

HP IQ, HP’s AI innovation lab, is seeking a Senior Power Systems Engineer to drive end-to-end system architecture, modeling, and optimization for wearable platforms. The role involves building power models, defining system use cases and operating modes, partnering with product and engineering teams to meet power targets, and defining manufacturing tests and field telemetry for new product introduction (NPI). The ideal candidate has strong systems thinking and hands-on experience with low-power architectures, and can build models and telemetry to guide tradeoffs from SoC to board level and maximize user runtime. The role works closely with product, hardware, firmware, manufacturing, and regression QA teams. The listed salary range is $170,000 to $240,000. HP IQ describes its work environment as flexible, with the freedom and flexibility to do your best work.

Requirements

Bachelor’s or Master’s degree in Electrical Engineering, Computer Science, or a related technical field.
At least 6 years of experience in power systems, systems engineering, or related domains.
Experience optimizing multi-core SoCs and understanding power systems at the platform or system level.
Experience building power models and correlating them with instrumented tests.
Ability to communicate technical concepts clearly and collaborate across engineering teams.

Nice To Haves

Experience with ARM-based embedded systems and profilers, including power supplies and power management ICs.
Experience with power and performance characterization, validation, and correlation to real system behavior using bench equipment and Python or MATLAB scripts.
Prior experience in computing platforms, servers, workstations, or embedded systems.
Demonstrated ability to influence system design decisions using data and analysis.
Experience working in a power-focused systems or architecture team.

Responsibilities

Own power architecture for a wearable device, including SoC states and sensor, audio, and memory architecture tradeoffs at board level.
Define and validate the battery, PCM, and charging profile.
Design power experiments, test plans, and measurement and telemetry mechanisms across firmware and hardware to optimize power and performance.
Build and maintain system-level power models for expected consumption across user profiles, map models by subsystem, and correlate modeled behavior with instrumented measurements.
Define user profiles, power and sleep states, and low-power operating modes.
Partner with product, hardware, firmware, manufacturing, and regression QA to align and execute toward power targets.