Senior Platform Safety Analysis Engineer, HALOs Platforms - Autonomous Vehicles

NVIDIA•US, SC, Remote, SC

36d•$224,000 - $356,500

About The Position

NVIDIA is developing a groundbreaking AI-based full stack for autonomous transportation and a base platform to support it. This requires a groundbreaking approach to functional safety in the underlying HALOs platform, including scheduling and management of synchronization and diverse HW compute engines, full platform error reporting and degradation, system state management and fail-operational features. We are seeking outstanding engineers to lead efforts developing the next generation of safe, AI-powered autonomous driving platforms. The focus is on functional safety of the underlying compute and communications platform on which NVIDIA's autonomous products are built. This role involves working at the confluence of NVIDIA's application stack and OEM vehicle platforms, developing and aligning safety architecture and requirements across NVIDIA and with customers.

Requirements

BS, MS or PhD in Computer Science, Computer Engineering, Electrical Engineering, or equivalent experience.
12+ years of experience in systems architecture or related fields.
Experience working across company boundaries as development partners.
Technically strong engineers with experience in safety analysis of embedded systems at the Hardware and Software Level.
Ability to find the right level of abstraction adapted to the tasks in hand.

Nice To Haves

Proven competence in performing safety analysis using qualitative and quantitative methods (e.g. FTA, FMEA and FMEDAs).
Background in HW SOC and/or board level architecture, Automotive ECU architecture is especially valued.
Demonstrable competence in tools and automation focused on safety analysis.
Familiarity with safety standards (ISO 26262, IEC 61508, ISO/PAS 21448).
Experience in the evaluation of fault metrics through the combination of built-in HW measures and application coverage.

Responsibilities

Propose new methods and refine existing practices for analyzing and demonstrating HW fault metric compliance, given the increased use of AI and underlying compute HW.
Carry out analysis using classical approaches such as fault trees alongside model-based techniques to derive application and system-level diagnostic measures on top of existing HW measures.
Develop automation to support the analysis of complex multi-layered systems.
Analyze and interpret internal and external safety documentation to identify improvements that can help meet challenging safety targets.
Ensure the integration of System, Software, and Hardware safety analysis methodologies to demonstrate the final system meets overall HW safety metrics.