Senior Photonics Engineer

Lyte • Sunnyvale, CA

3d • $210,000 - $280,000

About The Position

Lyte is seeking a senior Photonics Engineer to design silicon photonic devices, subcircuits, and photonic integrated circuits (PICs) for next-generation perception systems. As part of the Photonics Design and Architecture team, the engineer will translate architecture-level requirements—including optical link budgets, component specifications, and interface requirements—into optimized designs, validated simulation models, and tapeout-ready layouts. This hands-on technical role includes end-to-end ownership of assigned components and subcircuits, from simulation and layout through design verification, tapeout, and documentation. The engineer will work closely with the silicon team, which owns test and validation, and provide complete design handoffs to enable transfer to production.

The role also contributes to architecture definition, PDK development, automated engineering workflows, and optical and system integration. The engineer will collaborate with the III–V, packaging, IC, silicon, and operations teams to define and close interface requirements, support characterization, and improve designs and models based on measurement results.

Requirements

• M.S. or Ph.D. in electrical engineering, physics, optics, or a related discipline, or a B.S. with equivalent industry experience.
• 8+ years of relevant industry experience, or a Ph.D. with 5+ years of experience.
• Hands-on experience designing active and passive silicon or silicon nitride photonic components, with design ownership on multiple completed PIC tapeouts.
• Strong understanding of waveguide optics, semiconductor device physics, and fabrication-dependent device performance.
• Proficiency with electromagnetic simulation methods such as FDTD, eigenmode solvers, and eigenmode expansion (EME), as well as optical-circuit simulation using Lumerical, Tidy3D, or equivalent.
• Experience with schematic-driven layout in Cadence or Synopsys, foundry design rules, and pre-tapeout design verification, including LVS/DRC.
• Proficiency in Python for scientific computing, simulation automation, and data analysis.
• Ability to independently own designs from specification through tapeout, evaluate tradeoffs, and communicate results clearly to technical and cross-functional audiences.
• Experience using version control and maintaining organized, reproducible engineering work.

Nice To Haves

• Experience developing PCells, compact models, and PDK component libraries.
• Exposure to III–V devices and understanding of lasers and semiconductor optical amplifiers, including hybrid or heterogeneous integration with silicon photonics.
• Exposure to optical packaging, micro-optics, or free-space coupling.
• Experience correlating simulated device behavior with measured results.
• Familiarity with statistical variation analysis, such as Monte Carlo and corner analysis, and numerical optimization.
• Experience mentoring engineers or leading technical design reviews.

Responsibilities

• Design passive and active silicon and silicon nitride photonic components and subcircuits, including couplers, splitters, interferometers, polarization-management components, phase shifters, switches, and optical interfaces.
• Use electromagnetic, optical-circuit, and thermal simulations to predict device behavior and optimize performance against specifications for insertion loss, bandwidth, polarization response, footprint, power, and fabrication tolerance.
• Provide device-level performance models, simulation data, and tradeoff analyses to inform optical link budgets, component specifications, interface requirements, and performance margins.
• Implement component and subcircuit layouts in accordance with foundry design rules, run design-rule checks, and prepare design files for review and integration into full PIC layouts.
• Evaluate nominal performance, process sensitivity, and operating-condition limits; document assumptions, margins, and open risks; and present results in design reviews and cross-functional tapeout signoff.
• Develop and maintain parameterized cells (PCells), compact models, component documentation, and reusable design elements; update models and design guidance as characterization data become available.
• Build Python tools for simulation setup, parameter sweeps, optimization, layout generation, and data analysis, and maintain reproducible workflows and version-controlled design assets.
• Incorporate requirements for III–V sources, free-space coupling, packaging, thermal management, and electrical interfaces into device and subcircuit designs, working with the III–V, packaging, and IC teams to close interface requirements.
• Partner with the silicon team to define test structures, design-of-experiment (DOE) splits, and characterization objectives; provide predicted responses and measurement priorities; interpret results; and use findings to improve designs, models, and the PDK.
• Deliver design files, specifications, simulation results, interface requirements, and functional documentation to the silicon team for production transfer.
• Support the silicon and operations teams with technical questions and design revisions following handoff.

Benefits

• Competitive salary and equity
• Comprehensive medical, dental, and vision coverage
• 401(k) retirement plan
• Flexible vacation and time-off policy
• Collaborative, fast-paced, and inclusive work environment
• Opportunity to work on cutting-edge technologies with a highly cross-functional team

What This Job Offers

• Job Type: Full-time
• Career Level: Senior