Senior PDK Reliability Engineer

Intel Corporation•Santa Clara, CA

9d•$173,660 - $245,160•Hybrid

About The Position

Intel is shaping the future of technology to help create a better future for the entire world. Our work in pushing forward fields like AI, analytics, and cloud-to-edge technology is at the heart of countless innovations. With a career at Intel, you'll have the opportunity to use technology to power major breakthroughs and create enhancements that improve our everyday quality of life. Join us and help make the future more wonderful for everyone. Want to learn more? Visit our YouTube Channel or the link below. Life at Intel To support Intel Foundry strategy, we are looking for talents to join this exciting journey to drive design enablement in quality and reliability area on Intel leading technology nodes to build industry competitive design platform supporting customer design on Intel Si and package technologies. The general reliability design enablement includes PDK (Process Design Kits), TFM (tool/flow/methodology), Foundational IP (library, memory, analog IP) and DFR (Design for Reliability) to achieve best PPA (Power Performance Area) and reliability co-optimization. This role will be responsible for but not limited to: Definition and generation of reliability related PDK design rule and collateral covering all reliability mechanism, QA (quality assurance) and benchmarking analysis. Drive industry EDA (Electronic Design Automation) tool and flow enablement in synergy with PDK development, work with internal partners and EDA vendors to deliver competitive TFM to support design reliability verification. Competitive analysis and benchmarking technology reliability, plan and deliver industry leading PDK, design rule, design collateral, TFM and IP ecosystem to enable internal and external customer design on Intel technology.

Requirements

Bachelor's degree in electrical engineering, physics or a related field and 6+ years of relevant work experience or 4+ years of relevant experience and a master's degree, or a PhD degree with 2+ years of relevant experience.
3+ years' experience in one of the following areas: PDK development, reliability tool and flow, design for reliability, Circuit, IP and SOC design reliability validation using PDK, EDA tool and flow development.

Nice To Haves

Master's degree in electrical engineering, physics, or related field, or Ph.D. degree in electrical engineering, physics, or related fields.
Hands-on Experience on PDK development and validation; knowledge and understanding of PDK fundamentals; reliability design rules and their implementation in PDK and TFM.
Capability to use AI or program skills to write code, agent or script for design rule, techfile generation and quality assurance.
Experience on PDK, EDA tool/flow development, design flow application and interaction with IP and SOC design validation and sign-off; design impact and risk assessment in related reliability area.
Experience and knowledge on reliability verification and physics, such as aging including BTI (Bias Temperature Instability) and HCI (Hot Carrier Injection), Electro-Migration, high voltage design, EOS (Electrical Over-Stress), ESD (Electrostatic Discharge).
Experiences and skills in program management, stakeholder management, and strong communication skills.

Responsibilities

Definition and generation of reliability related PDK design rule and collateral covering all reliability mechanism, QA (quality assurance) and benchmarking analysis.
Drive industry EDA (Electronic Design Automation) tool and flow enablement in synergy with PDK development, work with internal partners and EDA vendors to deliver competitive TFM to support design reliability verification.
Competitive analysis and benchmarking technology reliability, plan and deliver industry leading PDK, design rule, design collateral, TFM and IP ecosystem to enable internal and external customer design on Intel technology.