Senior Microarchitecture Researcher

IonQ•Bothell, WA

About The Position

IonQ is seeking a Microarchitecture (uArch) Researcher to join a cross-functional team working to build quantum computers. The role focuses on the physical implementation, design, and layout of fault-tolerant architectures for ion trap quantum processors. You will implement, tailor, simulate, and design large-scale chip architectures that support fault-tolerant quantum computation, contributing to the physical and logical architecture of future quantum chips. You will take quantum error-correction protocols from theory to physical layouts for ion trap processors and develop simulation tools to assess those layouts under realistic noise. The work involves close collaboration with trap designers, AMO physicists, QEC researchers, and colleagues from a range of research backgrounds, as well as sharing results through research papers and other technical writing. The position requires four years of research experience in quantum computing or chip architecture and a degree in quantum computing, physics, engineering, chemistry, or a related field. Candidates should have strong expertise in at least one of AMO theory, QEC theory, QCVV theory, or classical VLSI theory, and be comfortable applying that expertise to real quantum hardware architecture. Candidates must also meet IonQ’s stated U.S. export-control and government-contract eligibility requirements.

Requirements

Four years of research experience in quantum computing or chip architecture.
A degree in quantum computing, physics, engineering, chemistry, or a related field.
Strong expertise in one or more of AMO theory, QEC theory, QCVV theory, or classical VLSI theory.
Comfort applying relevant expertise to the architecture of real quantum hardware.
Meet the stated U.S. export-control and government-contract eligibility requirements: qualifying U.S. Person status, or other authorization or license arrangements where applicable.

Nice To Haves

Strong expertise with quantum simulation techniques at the physical, gate, circuit, and QEC levels.
Experience with classical chip architecture and an interest in quantum chip architecture.
Experience with quantum error correction, logical operations, and decoders.
Ability to communicate with audiences ranging from the research community and business stakeholders to PhD-level colleagues.

Responsibilities

Contribute to the physical implementation of quantum error-correction protocols on ion trap processors.
Contribute to a library of simulation tools that analyze logical performance under realistic physical noise models.
Collaborate with trap designers, AMO physicists, QEC researchers, and colleagues from a broad range of research backgrounds.
Contribute to research papers and other technical writing.