Senior Mask Design Engineer - Hardware

NVIDIA•Santa Clara, CA

About The Position

NVIDIA has a history of reinvention, from pioneering the GPU in 1999 to fueling modern AI. The company operates as a "learning machine," constantly evolving to tackle challenging opportunities that impact the world. This position is for a Senior Mask Layout Design Engineer, joining a growing and multifaceted team responsible for groundbreaking high-speed mixed-signal circuit designs. The role offers a significant impact within an innovative, technology-focused company, contributing to product lines ranging from consumer graphics to self-driving cars and artificial intelligence.

Requirements

BSEE (or equivalent experience)
Minimum of 6 years of mask design / layout experience
Detailed knowledge of EDA tools from Cadence, Mentor and Synopsys.
Experience with floor planning, block level routing and large macro level assembly.
Background in running, debugging and ability to customize DRC and LVS decks such as Dracula, Hercules, Calibre.
Deep understanding of analog circuit layout concepts in submicron CMOS technologies.
Experience with analog layout for silicon chips in mass production.
Knowledge of high performance analog and high speed IO layout techniques such as common centroid layout, matching, symmetrical layout, signal shielding, use of dummy devices, thermal aware layout with consideration for electro migration and other analog specific guidelines.
Proficient in scripting languages like perl, python, skill etc.
Able to work effectively in a team, good social skills, excellent interpersonal skills (written and verbal) and brings passion and positive energy.

Responsibilities

Lead and implement IC physical layout for mixed-signal functions like high speed SerDes, Analog to Digital & Digital to Analog converters, Bandgaps, Regulators, References, Amplifiers, and various other building blocks of a successful IC design in groundbreaking sub-micron CMOS technologies using Cadence tools.
Work multi-functional with ASIC and mixed-signal engineers to customize designs for integration in VLSI products.
Take part in floor planning, custom layout and verifying against design rules and schematics.
Optimize circuit layouts to meet the specifications for system performance.
Work with design engineers by providing detailed floor plan and mentorship for matching and high-speed routings.
Provide support for post-silicon bring-up and debugging.