Senior Manufacturing and System Co-Design Workflow Engineer

NVIDIA•Us, CA

13h•Hybrid

About The Position

NVIDIA's Silicon Co-Design Group is seeking a Senior Manufacturing & System Co-Design Workflow Engineer to lead the methodology and infrastructure that maintains holistic, systematic alignment across the full portfolio of GPU, SoC, and CPU programs. This role involves defining manufacturing specification types, owning the workflow methodology, developing Python pipelines and automated checks to prevent specification drift, integrating SMAC work into end-to-end program management, and building agent-ready tooling and CI infrastructure. The goal is to ensure alignment between system specifications and manufacturing test specifications from pre-silicon through production release, preventing issues like escapes, yield loss, and performance loss. The strongest candidates will proactively design workflows and build automation to ensure long-term alignment.

Requirements

A BS, MS, or equivalent experience in Electrical Engineering, Computer Engineering, Computer Science, or Systems Engineering.
8+ years in system software, silicon bring-up, or productization engineering.
Strong Python and systems skills; experience shipping production services and data pipelines.
Deep understanding of the spec ecosystem: system POR, guard-bands, manufacturing screen specs, and test insertion constraints.
Proven track record of cross-org influence — methodologies others adopted, workflows redefined rather than simply operated within.
Ability to read silicon and productization outputs (speed, power, binning) and apply AI with genuine judgment: reviewable artifacts, and a clear view of where manual validation remains required.

Nice To Haves

Subject matter experts depending on an LLM-backed tool you built.
You've stood up a cross-org workflow from scratch and shipped automation that survived adoption across resistant partners, not as a proof of concept, but as infrastructure people actually depend on.
You think like a workflow architect: optimizing stages, runtime, and toil across the system, not closing tickets on a single program and moving on.
The strongest candidates are the ones who ship the fix, then immediately identify the next class of problems, and start designing for it before anyone else has noticed it's coming.

Responsibilities

Define manufacturing spec types, including schema and semantics, derived from system PORs and features.
Own the methodology that governs how specification work gets structured, versioned, and validated across the program lifecycle.
Develop production-grade Python pipelines and automated checks that catch specification drift between system POR and manufacturing test programs (ATE, SLT, BLT, L10+) before silicon exposes the discrepancy.
Wire SMAC work into the end-to-end program spine, milestones, gates, and artifacts, and define explicit TPM-driven attestation when checks lag.
Integrate tooling into an agent-ready harness: CLIs, MCPs, bug and spec retrieval, human-in-the-loop checkpoints, and evaluation-based CI gates running against real silicon workflows.
Drive adoption of SMAC methodology and tooling across Post Silicon (Prod), Operations, and DFX (DFT/DFP) teams.