Senior Manager, System Integration – Silicon Co-Design Group

NVIDIA•Santa Clara, CA

5d•Onsite

About The Position

The Silicon Co-Design Group (SCG) operates at the intersection of architecture, design, marketing, operations, and productization, covering early architecture through final product delivery across various markets including Datacenter, Gaming, Robotics, Automotive, and Embedded. System Integration is a critical function within SCG, serving as the point where architectural, design, software, and manufacturing decisions converge. This role involves leading the US-based System Integration team and collaborating with global teams. The position is central to the success of all NVIDIA silicon programs, setting the standard for system integration quality. Key challenges include identifying critical silicon issues earlier in the development cycle, often before software is production-ready, by shifting post-silicon coverage left and establishing wide-area testing as a repeatable capability. Additionally, the role requires developing strategies to maintain program milestones despite upstream dependencies like software, firmware, or methodology delays.

Requirements

Bachelor’s or Master’s in Electrical or Computer Engineering (or equivalent experience).
Over 12+ overall years of system-level post-silicon bring-up and debug experience.
5 years leading technical teams.
Shipped silicon experience.
Direct experience finding critical silicon issues before software was production-ready, including building or scaling wide-area or in-system test programs that ran in production.
Led technical teams across multiple geographies, with clear examples of attracting, growing, and retaining senior technical talent.
Strong EE fundamentals across DFT, digital design, computer architecture, power, timing, and fault analysis.
Ability to translate complex technical issues into clear options for executive audiences.

Nice To Haves

A history of process and methodology improvements that meaningfully lifted bring-up velocity, debug efficiency, or shipped silicon quality on programs you led.
Experience partnering deeply with a counterpart team in India or another major engineering hub — examples of building shared culture, shared metrics, and shared on-call across geographies.
DFT experience with system-test features for in-field test on production silicon, plus familiarity with fault models, DPPM, quality metrics, and RAS.
Concrete examples of redesigning how a team works with AI — faster analysis, smarter debug, automated reporting, or workflows the team adopted broadly.

Responsibilities

Plan and execute post-silicon feature integration, PVT validation, and wide-area testing across NVIDIA’s GPU, SoC, and CPU programs.
Build wide-area and in-system test as a repeatable capability that shifts post-silicon coverage left, so issues surface before we are production-ready.
Lead resolution of the most complex system-level issues, RMAs, and HW/SW interaction problems with creative workarounds and focused lab experimentation.
Develop new strategies to keep programs on milestone when upstream dependencies — software, firmware, methodology, validation — slip.
Hire, mentor, and retain senior technical talent. Build a strong bench and grow individual contributors into the next generation of senior technical leaders.
Partner across architecture, design, DFT, software, firmware, QA, and manufacturing teams.
Build operational rigor — bring-up tracking, debug forums, and a clear translation of execution data into structured, decision-ready options.