Senior Manager, Serdes Analog Design

Samsung Semiconductor•San Jose, CA

2d•$189,000 - $301,000•Onsite

About The Position

In this role, you will actively work on architecture and circuits of high-speed interconnect transceiver (Serdes). You will help define circuits and architecture for Serdes IPs, clock generation as well as traditional analog circuits. You’ll supervise designers to deliver the complete design and to support silicon validation and debugging. You’ll work with a team to develop high-performance and low-power serdes, including display interface, camera sensor interface, UCIe / die-to-die interconnect and 224/448Gbps UA-link/Ethernet using cutting-edge process technologies.

Requirements

Bachelors with 15+ years, Masters with 13+ years or PhDs with 10+ years of experience.
Minimum 7+ yrs experience in Analog/Serdes SoC design experience.
Knowledge and experience with analog circuits/mixed signal circuits: such as bandgap, LDO, filters.
Knowledge and experience with circuits of Serdes IPS: CTLE, DFE, FFE, clock distributions, PI, IQ generation.
Knowledge of Serdes architecture and high-speed interconnect standard (USB, PCIe, UCIe)
Well-versed in EDA tools (Cadence, Spectre, Totem, EMX)
Comfortable with scripting languages (Python, Matlab)

Nice To Haves

Knowledge and experience with ESD, PLL, clock generation, ADC, DAC is a big plus.

Responsibilities

Define architecture and circuits for serdes projects.
Supervise designers to complete the project and to conduct silicon validation.
Hands-on circuit design experience is a must.
Familiarity with low-power and low-voltage analog and custom digital circuit components using advanced CMOS process technologies
Translate component design specification to schematics.
Build simulation test-benches to evaluate circuit performance, functionality, power consumption and reliability.
Supervise layout of the complete project.
Optimize layout to improve the power consumption and performance of circuits